Verilog overview

Verilog Overview
MAHMOUD HAGHIGHI
WWW.POSEDGE.IR
VERILOG OVERVIEW12/20/2015 1

Overview
 Verilog Basics
 Simulation Tools

Overview
 A Hardware Description Language (HDL) is a language used to describe a
digital system, for example, a computer or a component of a computer.
 A digital system can be described at several levels:
 Switch level: wires, resistors and transistors
 Gate level: logical gates and flip flops
 Register Transfer Level (RTL): registers and the transfers of information
between registers.
 Two Major HDLs in Industry
• VHDL
• Verilog

Verilog vs. VHDL
VHDL
 “V” is short for Very High Speed Integrated Circuits.
 Designed for and sponsored by US Department of Defense.
 Designed by committee (1981-1985).
 Syntax based on Ada programming language.
 Was made an IEEE Standard in 1987.
Verilog
 Was introduced in 1985 by Gateway Design System Corporation, now a part of
Cadence Design Systems, Inc.'s Systems Division.
 Was made an IEEE Standard in 1995
 Syntax based on C programming language.
 Design examples using Verilog HDL
◦ Intel Pentium, AMD K5, K6, Atheon, ARM7, etc
◦ Thousands of ASIC designs using Verilog HDL

Design Methodology

Verilog HDL Models
 HDL model specifies the relationship between input signals and
output signals.
 In Verilog, A “module” contains the hardware description of the
circuit.
 Verilog code for a AND gate
Module definition
Ports definition
Module Structure

Numbers
 Numbers are specified using the following form
<size><base format><number>
 Examples:
◦ x = 347 // decimal number
◦ x = 4’b101 // 4- bit binary number 0101
◦ x = 16’h87f7 // 16-bit hex number h87f7
◦ x = 2’b101010
◦ x = 2’d83
size of the number in bits. ’b (binary)
’d (decimal)
’o(octal)
’h(hex).

operators
 Bitwise Operators
~ NOT
& AND
| OR
^ XOR
~| NOR
~& NAND
^~ or ~^ XNOR
 Logical & Relational Operators
!, &&, | |, ==, !=, >=, <=, >, <

Ports
 There are three different port types:
• Input
• Output
• Inout
 Port definition:
• <port type> <portwidth> <port name>
• Example:
A(7:0) B(7:0)
C
my_module
U1
A(7:0) B(7:0)
C

Data Types: Variables
 Two basic families of data types for variables: Nets and Registers
 Net variables – e.g. wire
• Memory less
• Variable used simply to connect components together
• Usually corresponds to a wire in the circuit.
 Register variables – e.g. reg
• Variable used to store data as part of a
behavioral description
• Like variables in ordinary procedural languages
 Note:
• reg should only be used with always and initial blocks (to be presented …)
• The reg variables store the last value that was procedurally assigned to them whereas
the wire variables represent physical connections between structural entities such as
gates.
A(7:0)
W(7:0)
C L K
A D
Fub1
U1
DA
CLK

Continuous Assignment
 Continuous statement is used to model combinational logic.
 A continuous assignment statement is declared as follows:
assign <net_name> = variable;
 assign corresponds to a connection.
 Target is never a reg variable.
 Examples:

Continuous Assignment
 Verilog code for a 4 bit adder:

Procedural Assignment
 Used for modeling sequential circuits.
 A procedural assignment statement is declared as follows:
Always @(event list) begin
<reg_name> <= variable;
end
 The assignment will be performed whenever one of the events in “event_list”
occurs.

Procedural Assignment
 Example: D-FF
D
clk
Out

Interconnecting Modules
 In order to use a module, it should be
instantiated:
<Module_name> <Instant_name> (<port mapping>)
 Example: using two mux2 to build a mux4
(actually this is not an mux4-1 !!!)
In(1 :0 ) O ut
se l
mux2_i1
mux2In4(3:0)
sel4(1:0)
In(1 :0 ) O ut
se l
mux2_i2
mux2
In4(3:2)
In4(1:0)
sel4[1]
sel4[0]
Out4(1:0)
w(1:0)
w[1]
w[0]
In4(3:0)
sel4(1:0)

Primitives
 No declaration required (predefined)
 Can only be instantiated
 Example: and a1 (C, A, B); //instance name
• Usually better to provide instance name for debugging.
 Example: or o1 (SET, ~A, C ),
o2(N, ABC,SET );
 Example: and #(10) a2(o, i1, i2); // name + delay

12/20/2015 VERILOG OVERVIEW 17
Test Bench
module <test module name> ;
// Data type declaration
// Instantiate module ( call the module that is going to be tested)
// Apply the stimulus
// Display results
endmodule
 Usefull commands:
• initial
• #delay
• forever
Tester
DUT
(Design
Under Test)
Test bench

Test Bench Example

Simulation Tools

Overview
 Simulation tools:
• Aldec Active-HDL
• Xilinx Isim
• Modelsim
• Altium Designer
• …
 Simulation Phases:
• Pre-synthesize (our talk)
• Post-synthesize
• Post-Place and root

Active HDL Tutorial
 Creating a simple project in Active HDL
 Step 1: Create a new workspace

Active HDL Tutorial
 Step 2: name your workspace

Active HDL Tutorial
 Step 3: Choose “Create an Empty Design with Design Flow”.

Active HDL Tutorial
 Step 4: Set default language to VERILOG

Active HDL Tutorial
 Step 5: Enter a name for your design

Active HDL Tutorial
 Step 6: Make a new Verilog Source

Active HDL Tutorial
 Step 7: follow the wizard

Active HDL Tutorial
 Step 8: Enter the name of your Verilog module

 Step 9: Add ports to your module
Active HDL Tutorial

Active HDL Tutorial
 Step 10: Add your code after port declaration (here the continuous
assignment for adder)

Active HDL Tutorial
 Step 11: Compile the module

Active HDL Tutorial
 Step 12: Initialize Simulation

Active HDL Tutorial
 Step 13: the software will ask you to select the Top-level module… do it!

Active HDL Tutorial
 In case you get this error…

Active HDL Tutorial
 Go to Design > Setting > Simulation > Verilog and uncheck “Verilog
Optimization”

Active HDL Tutorial
 Step 14: from File > New > Waveform open a new waveform window

Active HDL Tutorial
 Step 15: Select signals from the left window and Drag-and-Drop them to the
right

Active HDL Tutorial
 Step 16: Right click on any signal in the right panel and select Stimulators (if it
is already inactive, make sure initialization is performed)

Active HDL Tutorial
 Step 17: choose stimulator for input signala

Active HDL Tutorial
 Step 18: now you can run simulation by pressing “run for” button.

For more tutorials please visit our website
Click Here

Verilog overview

Recommended

More Related Content

What's hot (20)

Viewers also liked (20)

Similar to Verilog overview (20)

Recently uploaded (20)

Verilog overview