Synthesizing HDL using LeonardoSpectrum

Oct 14, 20143 likes1,123 views

This document discusses synthesizing HDL designs using the LeonardoSpectrum synthesis tool. It begins with an overview of synthesis and the basic synthesis process. It then describes the LeonardoSpectrum tool flow, including the stages of synthesis from technology independent to dependent. The document concludes with a tutorial on getting started with LeonardoSpectrum, walking through invoking the tool, loading a technology library, specifying input/output files, and setting global constraints.

Synthesizing HDL Using
Leonardo
Prepared By:
Eng. Hossam El-Sayed Abdel-Fadeel
2011

Goal
• Illustrate How to Synthesis your design
using LeonardoSpectrum Tool.

Outlines
• What is Synthesis?
• Basic synthesis process.
• Synthesis Tool flow.
• Synthesis stages.
• Getting Started with LeonardoSpectrum.

What is Synthesis?
• Once the design has been entered, it must be synthesized.
• The process of synthesis involves converting the VHDL source files into
a netlist.
• A netlist is simply a list of logical elements (things that combine,
change, or store digital signals) and a list of connections describing
how these elements are wired together.
• A netlist can be platform independent, that is, it can target any
architecture from any vendor. (e.g. Mentor LS tool, Synopsys).
• Many development environments provide additional support tools
such as Register Transfer Level (RTL) viewers (graphical
representations of the source code) and/or netlist viewers (graphical
representation of how the source code will be implemented in fabric).
• The Electronic Design Interchange Format (EDIF) is a more widely
accepted format.

Basic synthesis process
Initial HDL description
(technology independent)
RTL level
Logic level
Gate level
Final HDL description
(technology dependent
netlist)
Optimization
Optimization
Optimization
ASIC
PLD
Synthesis
directives

Synthesis Tool flow
HDL Designer
Synplify Pro Leonardo Spectrum
Design
Synthesis
Target ASIC/FPGA Implementation
Vendor
VHDL code
Netlist
Bitstream

Synthesis stages
Technology
independent
Compile Map Place & Route Implement
High level synthesis
Technology
dependent
Low level synthesis
- Code analysis
- Derivation of main
logic constructions
- Technology
independent
optimization
- Creation of “RTL
View”
- Mapping of extracted logic
structures to device
primitives
- Technology dependent
optimization
- Application of “synthesis
constraints”
-Netlist generation
- Creation of “Technology
View”
- Placement of
generated netlist onto
the device
-Choosing best
interconnect structure
for the placed design
-Application of
“physical constraints”
- Bitstream
generation
- Burning device

Synthesis stages
Technology
independent
Compile Map Place & Route Implement
High level synthesis Low level synthesis
Synplify Pro
Leonardo Spectrum
Technology
dependent

Synthesis Wizard Tutorial
• The following screens and four steps give you a tour of the
Synthesis Wizard. The steps ask you to apply example
choices and to use defaults.
– Step 1:Invoking LeonardoSpectrum
– Step 2: Load the technology library
– Step 3 - Input Files: *.vhd
– Step 4 - Global Constraints: *MHz
– Step 5 - Output File and Finish: *.edf (default)

Step 1:Invoking LeonardoSpectrum
• To start, invoke LeonardoSpectrum with Level 3

The Quick Setup Task Flow
1. Set Technology
3. Open Design Files
2. Set Working Directory
4. Set Clock
5. Set the Optimization Effort
6. Verify the Name and Destination
7. Activate Place and Route
8. “Click”

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Synthesizing HDL using LeonardoSpectrum

1. Synthesizing HDL Using Leonardo Prepared By: Eng. Hossam El-Sayed Abdel-Fadeel 2011

2. Goal • Illustrate How to Synthesis your design using LeonardoSpectrum Tool.

3. Outlines • What is Synthesis? • Basic synthesis process. • Synthesis Tool flow. • Synthesis stages. • Getting Started with LeonardoSpectrum.

4. What is Synthesis? • Once the design has been entered, it must be synthesized. • The process of synthesis involves converting the VHDL source files into a netlist. • A netlist is simply a list of logical elements (things that combine, change, or store digital signals) and a list of connections describing how these elements are wired together. • A netlist can be platform independent, that is, it can target any architecture from any vendor. (e.g. Mentor LS tool, Synopsys). • Many development environments provide additional support tools such as Register Transfer Level (RTL) viewers (graphical representations of the source code) and/or netlist viewers (graphical representation of how the source code will be implemented in fabric). • The Electronic Design Interchange Format (EDIF) is a more widely accepted format.

5. Basic synthesis process Initial HDL description (technology independent) RTL level Logic level Gate level Final HDL description (technology dependent netlist) Optimization Optimization Optimization ASIC PLD Synthesis directives

6. Synthesis Tool flow HDL Designer Synplify Pro Leonardo Spectrum Design Synthesis Target ASIC/FPGA Implementation Vendor VHDL code Netlist Bitstream

7. Synthesis stages Technology independent Compile Map Place & Route Implement High level synthesis Technology dependent Low level synthesis - Code analysis - Derivation of main logic constructions - Technology independent optimization - Creation of “RTL View” - Mapping of extracted logic structures to device primitives - Technology dependent optimization - Application of “synthesis constraints” -Netlist generation - Creation of “Technology View” - Placement of generated netlist onto the device -Choosing best interconnect structure for the placed design -Application of “physical constraints” - Bitstream generation - Burning device

8. Synthesis stages Technology independent Compile Map Place & Route Implement High level synthesis Low level synthesis Synplify Pro Leonardo Spectrum Technology dependent

9. Getting Started with

10. Synthesis Wizard Tutorial • The following screens and four steps give you a tour of the Synthesis Wizard. The steps ask you to apply example choices and to use defaults. – Step 1:Invoking LeonardoSpectrum – Step 2: Load the technology library – Step 3 - Input Files: *.vhd – Step 4 - Global Constraints: *MHz – Step 5 - Output File and Finish: *.edf (default)

11. Step 1:Invoking LeonardoSpectrum • To start, invoke LeonardoSpectrum with Level 3

12. Main Window at Startup

13. Main Window at Startup

14. Main Window Toolbar Synthesis Bar

15. Device Settings

16. Step 2: Load the technology library

17. The Quick Setup Task Flow 1. Set Technology 3. Open Design Files 2. Set Working Directory 4. Set Clock 5. Set the Optimization Effort 6. Verify the Name and Destination 7. Activate Place and Route 8. “Click”

18. Step 3: Input Files

19. Set Working Library

20. Step 4: Global Constraints

21. Step 5: Output File and Finish

Synthesizing HDL using LeonardoSpectrum

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