Crash course in verilog

Summary of Course Why do I need HDLs? What are HDLs? How do I use HDLs? Where do I get more information?

Why Do You Need HDLs? Ability to handle large, complex designs Different levels of abstraction Reusability Concurrency Timing Optimization Standards Documentation

What Are HDLs? Verilog VHDL ABEL CUPL PALASM

FSM - HDL Entry // This module is used to implement the memory control state machine module state_machine(sysclk, input1, input2, state3); /* INPUTS */ input sysclk; // system clock input input1, input2; // inputs from the adder /* OUTPUTS */ output state3; // this can be used as the write signal /* DECLARATIONS */ wire ps1; // input to state1 flip-flop wire ps2; // input to state2 flip-flop wire ps3; // input to state3 flip-flop reg state1, state2, state3; // state bits assign ps1 = ~state2 & ~state3; assign ps2 = state1 & input1 & input2; assign ps3 = state2 | (state3 & input1); initial begin // initialize the state machine state1 = 0; state2 = 0; state3 = 0; end always @(posedge sysclk) begin // clock in the new state on the state1 <= #3 ps1; // rising edge of sysclk state2 <= #3 ps2; state3 <= #3 ps3; end endmodule

Advantages of HDLs Multiple levels of abstraction Reusability Concurrency Timing Optimization Standards Documentation Large, complex designs

Levels of Abstraction Behavioral models Algorithmic Architectural Structural models Register transfer logic (RTL) Gate level Switch level

Reusability Code written in one HDL can be used in any system that supports that HDL. of 88

Concurrency Unlike standard programming languages, HDLs perform concurrent execution of statements. Necessary for hardware simulation. of 88

Explicit Timing module state_machine(sysclk, input1, input2, state3); . . . // Output delays are specified with the # symbol assign ps1 = #10 ~state1 & ~state2; assign ps2 = #5 state1 & input1 & input2; assign ps3 = #12 state2 | (state3 & input1); initial begin // initialize the state machine #13; // wait 13 time units before initializing state1 = 0; state2 = 0; state3 = 0; end always @(posedge sysclk) begin state1 <= #3 ps1; // output delay = 3 time units state2 <= #3 ps2; state3 <= #3 ps3; end endmodule

Optimization Synthesis friendly

Standards VHDL U.S. Department of Defense IEEE-STD-1076 Verilog Open Verilog International (OVI) IEEE-STD-1364

Documentation Text-based, programming-type languages. Lend themselves easily to documentation.

Large, Complex Designs Large, complex designs require all of the previous features. HDLs are much better suited to large, complex designs than schematic capture or any other methods of design currently available.

How Do I Use Verilog? Basic Verilog syntax Register, net, and parameter data types Modules Operators and expressions Continuous assignments Execution control statements Functions and tasks Procedural blocks Compiler directives System tasks and functions

Basic Verilog Syntax Comments Integer and real number constants String constants Logic values Identifiers Special tokens

Comments Same format as C++ Single line comments begin with a // and end at the end of the line // This is a comment Enclose the comments between /* and */ /* This is also a comment */

Integer Constants <size>’<base><value> where <size> is the number of bits. If left out, the default value of 32 bits is used <base> is b, o, d, or h for binary, octal, decimal, or hexadecimal. If left out, the default is decimal <value> is any legal number for the specified base. A ‘ z ’ or a ‘ ? ’ instead of a digit represents a high impedance signal in an integer. An ‘ x ’ instead of a digit in an integer represents an undefined signal of 88

Integer Constants 171 - size = 32, base = 10 ’ h2f3 - size = 32, base = 16 12’b1111_0000_1011 - size = 12, base = 2 3’b11? - size = 3, base = 2, 16’O101342 - size = 16, base = 8 8’hZ - size = 8, base = 16 of 88

Real Number Constants 10.5 - decimal notation 3.1415926 - decimal notation 9.3e-3 - scientific notation 7.7e12 - scientific notation of 88

String Constants Used to generate output from the simulator Enclosed in double quotes and must be on a single line Same escape characters as C: \t tab \n newline \\ backslash \” double quote %% percent sign of 88

Logic Values Four values - 0, 1, x, z Unknown values - x, L, H of 88

Identifiers Legal identifiers john_smith JohnSmith1 _john2john \@my_house#3 Illegal identifiers 2JohnSmith John*2 of 88

Data Types Nets Registers Parameters of 88

Special Tokens Built-in functions $ - System tasks and functions # - Delay values for simulation ` - Compiler directives of 88

Nets Wires connected to outputs of devices. When the output changes, the value of the net immediately changes. of 88

Net Types wire, tri standard interconnect wires wor, trior multiple drivers in a Wire-OR wand, triand multiple drivers in a Wire-AND trireg capacitive storage tri1 pulled up when not driven tri0 pulled down when not driven supply0 ground net (always 0) supply1 power net (always 1) of 88

Declarations of Nets wire reset; // This is a single signal tri1 [4:0] address; /* This is a bus consisting of 5 signals that are pulled up */ of 88

Registers Hold their values until a new value is explicitly assigned Used in behavioral models and simulations (and flip-flops) of 88

Register Data Types reg unsigned integer variable of any specified width integer signed integer variable, 32 bits wide real signed floating-point variable, double precision event boolean time unsigned integer variable, 64 bits wide of 88

Declarations of Registers integer i, j, count; real x, y, val; event trigger, flag_set; time t_setup, t_hold; reg [15:0] data; of 88

Parameters Run-time constants module temp(in1, in2, out); . . . parameter p1 = 5; . . . wire [p1:0] signal1; // A wire declaration using parameter reg store1, store2; . . . store1 = p1 & store2; // An equation using a parameter . . . endmodule of 88

Modules The essential building blocks for modeling hardware. Represents a self-contained device within the design. May be a state machine within an ASIC, an entire ASIC, or a complete system. of 88

Nested Modules of 88 A Crash Course in Verilog

Primitives Primitive Function Expandable? not(out, in) inverter expandable outputs buf(out, in) buffer expandable outputs and(out, in1, in2) logical AND expandable inputs or(out, in1, in2) logical OR expandable inputs xor(out, in1, in2) logical EX-OR expandable inputs nand(out, in1, in2) logical NAND expandable inputs nor(out, in1, in2) logical NOR expandable inputs xnor(out, in1, in2) logical EX-NOR expandable inputs bufif1(out, a, e) tri-state buffer enable = 1 not expandable bufif0(out, a, e) tri-state buffer enable = 0 not expandable notif1(out, a, e) tri-state inverter enable = 1 not expandable notif0(out, a, e) tri-state inverter enable = 0 not expandable of 88 A Crash Course in Verilog

Primitive Delay bufif0 #(3,3,7) (out, in, ctrl); // rise, fall, turn-off times and #(2,3) (out, in1, in2); // rise, fall or #(3.2:4.0:6.3) o1(out, in1, in2); // min:typ:max nand #(1:2:3, 2:3:4) n1(out, in1, in2); // rise min:typ:max, // fall min:typ:max of 88

Operators Symbol Operator type + - * / arithmetic > >= < <= relational ! && || logical == != logical equality ?: conditional % modulus === !== case equality ~ & | ^ ~^ bit-wise & ~& | ~| ^ ~^ unary reduction << >> shift of 88

Operator Precedence Operator Precedence ! & ~& | ~| ^ ~^ + - (unary operators) highest * / % + - << >> < <= > >= == != === !== & ~& ^ ~^ | ~| && || ?: lowest of 88

Concatenation & Replication Curly brackets Acts like parentheses Concatenate nets into a wider net a = {2 ’ b11, 4 ’ h6}; // concatenation a = {2{3 ’ b110}}; // replication a = 6 ’ b110110; of 88

Unary Reduction Take a bus and operate on all bits to reduce it to a single bit Unary XNOR: ~^4 ’ b0110 is reduced to 1 ’ b1 of 88

Procedural Assignments Assigns values to registers. Evaluated only when the statement is executed. Used for clocked logic (e.g., flip-flops and state machines) and behavioral models. of 88

Procedural Assignment Examples assign cnt = cnt + 1; // Optional assign statement num = cnt/2; // Result truncated to an integer x = 157.3; assign y = x/2; zCount = 1.2e-5; of 88

Continuous Assignments Assigns values to nets. Continuously being evaluated. Used to model combinatorial logic. of 88

Continuous Assignment Examples wire out1; // out1 is declared as a wire assign out1 = in1 & ~in2; // continuous assignment – // whenever in1 or in2 changes, // out1 will also change wire [7:0] net1 = in1 ^ in2; // declaration and assign // statement assign #5 out1 = in1 | in2; // assignment with delay - out1 // changes 5 time units after // in1 or in2 change of 88

Execution Control Statements Timing control statements Conditional statements Looping statements of 88

Timing Control Statements Simple delay Event-triggered delay Level-triggered delay Intra-assignment timing control Blocking and non-blocking assignments of 88

Simple Delay Wait a certain amount of time before executing code Specified with the pound (#) symbol initial begin #1 $display(“%0d HELLO”, $time); #2 $display(“%0d world!”, $time); end of 88

Event-triggered Delay An event is an occurrence at one time during simulation. Based on when this event happens, other code can execute. Use @ symbol to hold off executing the following statement until the specified event has occurred. Useful for modeling interrupts. of 88 A Crash Course in Verilog

Event-triggered Delay ->event1 // event trigger @event1 var = 0; // execute when // event1 is true @(posedge clk) a = 1; // execute on the // 0-to-1 transition // of the signal clk @(negedge reset) a = 0; // execute on the // 1-to-0 transition // of reset signal @(posedge clk or negedge reset) b = 0; // execute on // either of these // conditions of 88 A Crash Course in Verilog

Level-triggered Delay Similar to event-triggered delay. Any condition can be used to begin executing the following code. Uses a WAIT statement with an expression in parentheses. When the expression becomes true, the code executes. The code executes only once, even if the expression remains true. of 88 A Crash Course in Verilog

Level-triggered Delay wait(a === 1) $display(“%0d HELLO”, $time); wait(a === 2) $display(“%0d there”, $time); wait(a === 3) $display(“%0d world!”, $time); of 88 A Crash Course in Verilog

Intra-assignment Timing Avoids race conditions. Places the delay inside the assignment statement. Verilog evaluates the right hand side of the equation immediately and stores the value. When the specified time arrives it assigns that value. of 88 A Crash Course in Verilog

Intra-assignment Timing Race Condition module race(clock); input clock; reg a, b; initial begin a = 0; b = 1; end // At 5 time units after the clock edge, there is a race // between a and b. We don’t know what the final value will // be, or there may be an infinite loop. always @(posedge clock) begin #5 a = b; end always @(posedge clock) begin #5 b = a; end endmodule of 88 A Crash Course in Verilog

Intra-assignment Timing No Race Condition module no_race(clock); input clock; reg a, b; initial begin a = 0; b = 1; end // At the clock edge, the future values of a and b are // determined and stored. At 5 time units after the clock // edge, a and b are assigned the stored values. There is no // race condition. always @(posedge clock) begin a = #5 b; end always @(posedge clock) begin b = #5 a; end endmodule of 88 A Crash Course in Verilog

Blocking and Non-blocking Assignments Blocking assignments block the remaining code from executing until a delay has passed Non-blocking assignments set up the output to change at a future time, and continue executing the next statements of 88 A Crash Course in Verilog

Blocking and Non-blocking Assignments Blocking assignments ff1 = #3 ff2; // ff1 changes at time 3 ff2 = #3 ~ff1; // ff2 changes at time 6 Non-blocking Assignments ff1 <= #3 ff2; // Both flip-flops change // simultaneously at time 3 ff2 <= #3 ~ff1; // with no race conditions. of 88 A Crash Course in Verilog

The D Flip-Flop of 88 A Crash Course in Verilog

Conditional Statements If and if-else statement Case statement of 88 A Crash Course in Verilog

If and If-else Statement if (a > b) begin // beginning of outer if // begin-end allows multiple // statements to be executed by the // if statement b = b + 1; if (a == b) // beginning of inner if flag = 1; else begin // else belongs to inner if flag = 0; count = count + 1; end end of 88 A Crash Course in Verilog

Case Statement case (addr) // beginning of case statement 2’b00 : data = x; 2’b01 : data = y*2; 2’b0x : x = 3; // must match exactly 2’b0z : y = 1; // must match exactly default : // execute this statement if none of // the other cases are true (optional) begin data = 0; x = 0; y = 0; end endcase // this ends the case statement of 88 A Crash Course in Verilog

Looping Statements Repeat loop While loop For loop of 88 A Crash Course in Verilog

Repeat Loop Executes the following statement a fixed number of times. Example: repeat(100) $display(“I will not chew gum in class!”); of 88 A Crash Course in Verilog

While Loop Executes code as long as the specified condition is true Example: count = 10; // initialize count // stupid way to zero count while (count > 0) count = count - 1; while (count < 10) begin // execute code while count<10 count = count + 1; // increment count $display(“Count = %0d”, count); #10; // delay 10 time units end of 88 A Crash Course in Verilog

For Loop Executes code as long as the specified condition is true Sets up initial conditions and conditions to be executed on each loop Example: // execute code while count < 10 for (count = 0; count < 10; count = count + 1) begin $display(“Count = %0d”, count); #10; end of 88 A Crash Course in Verilog

Functions and Tasks Small sections of frequently used code. Tasks Can contain any kind of code and any number of inputs and outputs. Can contain delays Functions Cannot include any delay information. Executed in zero time (simulation time). Must have at least one input Must have exactly one output. of 88 A Crash Course in Verilog

Functions module test_module; reg [7:0] input; reg [7:0] filter; reg output; . . . output = test_function(input, filter); . . . function test_function; // this is the function declaration input [7:0] data; // these are the inputs input [7:0] mask; reg temp; // this is an internal register begin // begin the function logic temp = data & mask; if (temp > 16) test_function = 1; // this is the output else test_function = 0; // this is the output end endfunction endmodule of 88 A Crash Course in Verilog

Tasks module test_module; reg [7:0] input; reg out1; reg [7:0] out2; . . . test_task(input, out1, out2); . . . task test_task; // this is the task declaration input [7:0] in_data; // these are the inputs output out_data1; // these are the outputs output [7:0] out_data2; out_data1 = #3 ^in_data; out_data2 = #2 in_data & 8’h7E; endtask endmodule of 88 A Crash Course in Verilog

Procedural Blocks Initial block begins with the keyword initial executes exactly once at time 0 Always block begins with the keyword always executes each time the condition following the always keyword is met Typically uses a begin-end construct or a fork-join construct of 88 A Crash Course in Verilog

Procedural Blocks module procedures; reg a, b, c, d; // initial block with a begin-end construct initial begin a = 0; b = 0; c = 0; d = 0; end always @(posedge clock) begin // always block with begin-end a = #3 ~b; // a changes at time 3 b = #3 ~c; // b changes at time 6 end always @(posedge clock) fork // always block with fork-join c = #3 ~b; // both c and d change // simultaneously at time 3 d = #3 ~a; // (watch for race conditions). join endmodule of 88 A Crash Course in Verilog

Compiler Directives `timescale sets the time unit and its precision ìnclude include other files `define defines compile-time constants ìfdef èlse èndif selectively compile code of 88 A Crash Course in Verilog

System Tasks & Functions $time a variable that holds the current simulation time $display creates formatted output to the screen $monitor output variables only when they change $stop stop simulating and enter debug mode $finish finish the simulation of 88 A Crash Course in Verilog

Coding Guidelines Code template Comments Signal Definitions Code Sections Modules of 88 A Crash Course in Verilog

Code Template /*********************************************************/ // MODULE: Code template // // FILE NAME: template.v // VERSION: 1.0 // DATE: January 1, 2003 // AUTHOR: Bob Zeidman, Zeidman Consulting // // CODE TYPE: RTL or Behavioral Level // // DESCRIPTION: This template is used to have a coding // standard for each Verilog module. // /*********************************************************/ // DEFINES // TOP MODULE // PARAMETERS // INPUTS // OUTPUTS // INOUTS // SIGNAL DECLARATIONS // ASSIGN STATEMENTS // MAIN CODE of 88 A Crash Course in Verilog

Header Module name File name Version number Creation date Code author Code type (e.g., RTL, Behavioral) Short description of function Modification dates Modification descriptions of 88 A Crash Course in Verilog

Signal Definitions Description of each signal where it is first defined Keep each signal on a separate line Line up comments for easier reading of 88 A Crash Course in Verilog

Code Sections Begin each section with a general description Sections include always blocks initial blocks if statements while loops case statements etc. Comment each execution branch Module name comment at end of module of 88 A Crash Course in Verilog

Comments As many comments as possible There are never too many comments Comments should be meaningful of 88 A Crash Course in Verilog

Summary Why do you need HDLs. What are HDLs. How to use HDLs (Verilog). Where to get more information.

Where to Get Information Zeidman, Bob, Verilog Designer's Library , Prentice-Hall, 1999 Palnitkar, Samir, Verilog HDL: A Guide to Digital Design and Synthesis , Prentice-Hall, 1996 Navabi, Zainalabedin, Verilog Digital System Design , McGraw Hill Text, 1999 Moorby, P. R., and Thomas, D. E., The Verilog Hardware Description Language , Kluwer Academic Publishers, 1998 Bhasker, J., Verilog HDL Synthesis, A Practical Primer , Star Galaxy Press, 1998 Bhasker, J., A Verilog HDL Primer , Star Galaxy Press, 1998

Where to Get Information On the Internet Introduction to Verilog (www.ZeidmanConsulting.com) EDA Industry Working Groups (www.EDA.org) KnowHow (www.doulos.com/knowhow) Alternate Verilog FAQ, Rajesh Bawankule (www.angelfire.com/in/verilogfaq) Rajesh Bawankule's Verilog and EDA page (www.angelfire.com/in/rajesh52/verilog.html) of 88 A Crash Course in Verilog

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Crash course in verilog

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