FPGA training session generic package and funtions of VHDL by Digitronix Nepal

FPGA Training Session
Himalaya College of Engineering
FPGA-ARM Training Session HCOE
In Association with

VHDL: Generic , Package and
Functions

Generic
ENTITY and2 IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT( a, b : IN BIT;
PORT( c : OUT BIT);
END AND2;
ARCHITECTURE load_dependent OF and2 IS
SIGNAL internal : BIT;
BEGIN
internal <= a AND b;
c <= internal AFTER (rise + (load * 2 ns)) WHEN internal = ‘1’
ELSE internal AFTER (fall + (load * 3 ns));
END load_dependent;
• Generics are a general mechanism used
to pass information to an instance of an
entity.
• The information passed to the entity can
be of most types allowed in VHDL.
• Generics cannot be assigned information
as part of a simulation run.
• The information contained in generics
passed into a component instance or a
block can be used to alter the simulation
results, but results cannot modify the
generics.

Generic: Structural Modeling
ENTITY and2 IS
PORT( a, b : IN BIT;
PORT( c : OUT BIT);
END AND2;
ARCHITECTURE load_dependent OF and2 IS
SIGNAL internal : BIT;
BEGIN
internal <= a AND b;
c <= internal AFTER (rise + (load * 2 ns)) WHEN internal = ‘1’
ELSE internal AFTER (fall + (load * 3 ns));
END load_dependent;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY test IS
PORT ( ina, inb, inc, ind : IN std_logic;
PORT ( out1, out2 : OUT std_logic);
END test;
ARCHITECTURE test_arch OF test IS
COMPONENT AND2
PORT ( a, b : IN std_logic;
PORT ( c : OUT std_logic);
END COMPONENT;
BEGIN
U1: AND2 GENERIC MAP(10 ns, 12 ns, 3 )
PORT MAP (ina, inb, out1 );
U2: AND2 GENERIC MAP(9 ns, 11 ns, 5 )
PORT MAP (inc, ind, out2 );
END test_arch;

Package
• The primary purpose of a package is to encapsulate elements that can be
shared (globally) among two or more design units.
• A package is a common storage area used to hold data to be shared among
a number of entities.
• Declaring data inside of a package allows the data to be referenced by
other entities; thus, the data can be shared.
• A package consists of two parts: a package declaration section and a
package body.
• The package declaration defines the interface for the package, much the
same way that the entity defines the interface for a model.
• The package body specifies the actual behavior of the package in the same
method that the architecture statement does for a model.

Package USE LIBRARY IEEE;
PACKAGE math IS
TYPE st16 IS ARRAY(0 TO 15) OF std_logic;
FUNCTION add(a, b: IN st16) RETURN st16;
FUNCTION sub(a, b: IN st16) RETURN st16;
END math;
PACKAGE BODY math IS
FUNCTION vect_to_int(S : st16) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
BEGIN
FOR i IN 0 TO 7 LOOP
result := result * 2;
IF S(i) = ‘1’ THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END vect_to_int;
FUNCTION int_to_st16(s : INTEGER) RETURN st16 IS
VARIABLE result : st16;
VARIABLE digit : INTEGER := 2**15;
VARIABLE local : INTEGER;
BEGIN
local : = s;
FOR i IN 15 DOWNTO 0 LOOP
IF local/digit >>= 1 THEN
result(i) := ‘1’;
local := local - digit;
ELSE
result(i) := ‘0’;
END IF;
digit := digit/2;
END LOOP;
RETURN result;
END int_to_st16;
FUNCTION add(a, b: IN st16) RETURN st16 IS
VARIABLE result : INTEGER;
BEGIN
result := vect_to_int(a) + vect_to_int(b);
RETURN int_to_st16(result);
END add;
FUNCTION sub(a, b: IN st16) RETURN st16 IS
VARIABLE result : INTEGER;
BEGIN
result := vect_to_int(a) - vect_to_int(b);
RETURN int_to_st16(result);
END sub;
END math;
• Following is an
example of a
complete
package
making use of
this feature

Package: Block Statements
LIBRARY IEEE;
PACKAGE bit32 IS
TYPE tw32 IS ARRAY(31 DOWNTO 0) OF std_logic;
END bit32;
LIBRARY IEEE;
USE WORK.bit32.ALL;
ENTITY cpu IS
PORT( clk, interrupt : IN std_logic;
PORT( addr : OUT tw32; data : INOUT tw32 );
END cpu;
ARCHITECTURE cpu_blk OF cpu IS
SIGNAL ibus, dbus : tw32;
BEGIN
ALU : BLOCK
SIGNAL qbus : tw32;
BEGIN
-- alu behavior statements
END BLOCK ALU;
REG8 : BLOCK
SIGNAL zbus : tw32;
BEGIN
REG1: BLOCK
SIGNAL qbus : tw32;
BEGIN
-- reg1 behavioral statements
END BLOCK REG1;
-- more REG8 statements
END BLOCK REG8;
END cpu_blk;
• Blocks are a partitioning mechanism
within VHDL that allow the designer
to logically group areas of the model.
• The statement area in an architecture
can be broken into a number of
separate logical areas.
• For instance, if you are designing a
CPU, one block might be an ALU,
another a register bank, and another
a shifter.
• Each block represents a self-
contained area of the model.
• Each block can declare local signals,
types, constants, and so on.
• Any object that can be declared in the
architecture declaration section can
be declared in the block declaration
section.

Subprograms: Procedures and Functions
• A procedure can return more than one argument; a function always
returns just one.
• In a function, all parameters are input parameters; a procedure can
have input parameters, output parameters, and inout parameters.
• There are two versions of procedures and functions: a concurrent
procedure and concurrent function, and a sequential procedure and
sequential function.
• All statements inside of a subprogram are sequential.

Procedures
USE LIBRARY IEEE;
PROCEDURE vector_to_int (z : IN std_logic_vector;
x_flag : OUT BOOLEAN; q : INOUT INTEGER) IS
BEGIN
q := 0;
x_flag := false;
FOR i IN z’RANGE LOOP
q := q * 2;
IF z(i) = ‘1’ THEN
q := q + 1;
ELSIF z(i) /= F0 THEN
x_flag := TRUE;
END IF;
END LOOP;
END vector_to_int;
• Conversion from
an array of a
multivalued
type to an
integer

Function: Package
USE LIBRARY IEEE;
PACKAGE num_types IS
TYPE log8 IS ARRAY(0 TO 7) OF std_logic; --line 1
END num_types;
USE LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE WORK.num_types.ALL;
ENTITY convert IS
PORT(I1 : IN log8; --line 2
O1 : OUT INTEGER); --line 3
END convert;
ARCHITECTURE behave OF convert IS
FUNCTION vector_to_int(S : log8) --line 4
RETURN INTEGER is --line 5
VARIABLE result : INTEGER := 0; --line 6
BEGIN
FOR i IN 0 TO 7 LOOP --line 7
result := result * 2; --line 8
IF S(i) = ‘1’ THEN --line 9
result := result + 1; --line 10
END IF;
END LOOP;
RETURN result; --line 11
END vector_to_int;
BEGIN
O1 <= vector_to_int(I1); --line 12
END behave;
• The following
example is a
function that
takes in an array
of the std_logic
type- “Standard
Logic Package”
and returns an
integer value

Function: Package USE LIBRARY IEEE;
ENTITY dff IS
PORT(d, clk : IN std_logic;
PORT(q : OUT std_logic);
FUNCTION rising_edge(SIGNAL S : std_logic) --line 1
RETURN BOOLEAN IS --line 2
BEGIN
--this function makes use of attributes
--‘event and ‘last_value discussed
--in Chapter 6
IF (S’EVENT) AND (S = ‘1’) AND --line 3
(S’LAST_VALUE = ‘0’) THEN --line 4
RETURN TRUE; --line 5
ELSE
RETURN FALSE; --line 6
END IF;
END rising_edge;
END dff;
ARCHITECTURE behave OF dff IS
BEGIN
PROCESS( clk)
BEGIN
IF rising_edge(clk) THEN --line 7
q <= d; --line 8
END IF;
END PROCESS;
END behave;
• Following is an
example
showing a
function that
contains signal
parameters.
• provides a rising
edge detection
facility for the D
flip-flop being
modeled

Reference
• DL Perry “VHDL programming”
• Pong P Chu “FPGA design with VHDL”

FPGA-ARM Training Session HCOE
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FPGA training session generic package and funtions of VHDL by Digitronix Nepal

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FPGA training session generic package and funtions of VHDL by Digitronix Nepal