8259 programmable interrupt controller

8259 Programmable Interrupt Controller T.Srikrishna,M.Sc,M.Tech,GVP
8259 (PIC)
• 8085 Processor has only 5 hardware interrupts.
• Consider an application where a number of I/O devices connected with CPU desire to transfer
data. In this process more number of interrupt pins are required.
• In these multiple interrupt systems the processor will have to take care of priorities.
Features:
 Able to handle a number of interrupts at a time.
 Takes care of a number of simultaneously appearing interrupt requests along with their types and
priorities.
 Compatible with 8-bit as well as 16-bit processors.
 8 levels of interrupts.
 Can be cascaded in master-slave configuration to handle 64 levels of interrupts.
 Internal priority resolver.
 Fixed priority mode and rotating priority mode.
 Individually maskable interrupts.
 Accepts IRQ, determines priority, checks whether incoming priority > current level being
serviced, issues interrupt signal.
 No clock required.
Pin Diagram
It includes 8 blocks.
• Control logic
• Read/Write logic
• Data bus buffer
• Three registers (IRR,ISR and IMR)
• Priority resolver

• Cascade Buffer
READ/WRITE LOGIC
This is a typical read/write control logic. When A0 is low, the controller is selected to write a command.
The chip select and A0 is used for determining port address.
CONTROL LOGIC
This has 2 pins INT(interrupt) and INTA(bar)(interrupt acknowledge) as input.
The INT is connected to MPU. Whereas the INTA(bar) is interrupt acknowledege
from MPU.
CASCADED BUFFER/COMPARATOR
this is used to expand number of interrupts levels by cascading 2 or more 8259’s.
The associated three I/O pins (CAS0- 2) are outputs when the 8259 is used as a master and are
inputs when the 8259 is used as a slave. As a master, the 8259 sends the ID of the interrupting
slave device onto the CAS0 - 2 lines. The slave, thus selected will send its preprogrammed
subroutine address onto the Data Bus
Interrupt Request Register (IRR) and In-Service Register (ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request
Register (lRR) and the In- Service Register (lSR). The IRR is used to indicate all the interrupt
levels which are requesting service, the request are stored in the register.
and the ISR is used to store all the interrupt levels which are currently being serviced

Priority Resolver
This logic block determines the priorities of the bits set in the lRR. The highest priority is selected
and strobed into the corresponding bit of the lSR during the INTA sequence.
Interrupt Mask Register (IMR)
The IMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the
output of the IRR. Masking of a higher priority input will not affect the interrupt request lines of
lower priority
A0: This input signal is used in conjunction with WR* and RD* signals to write commands into the
various command registers, as well as reading the various status registers of the chip. This line can be
tied directly to one of the address lines
The events occur as follows in a 8085 system.
1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the corresponding
IRR bit (s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an INTA* pulse.
4. Upon receiving an INTA* from the CPU group, the highest priority ISR bit is set, and the
corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the
8-bit Data Bus through its D7-0 pins.
5. This CALL instruction will initiate two more INTA* pulses to be sent to the 8259A from the CPU group.
6. These two INTA* pulses allow the 8259A to release its pre-programmed subroutine address onto the
Data Bus. The lower 8-bit address is released at the first INTA* pulse and the higher 8-bit address is
released at the second INTA* pulse.
7. This completes the CALL instruction released by the 8259A.
A counter is a device that records the number of occurrences of a particular event. In
modern applications, counters are based on electronic devices and the counters are
sequential logic circuit designed to record the number of electric pulses fed into the counter.

• A timer is an application of the counters where a certain signal with a fixed frequency
(hence period) is counted to record the time.
A timer measures time, a counter counts events. So a timer with a 1MHz clock could tell you
how many clock cycles occurred between two events or how many microseconds. A counter
could be used to count events i.e. tell you how many events have occured.
 Temperature measurement is used in variety of applications like furnace, water bath, oven, etc.
with the help of transducers like thermocouple.
 The output of thermocouple is proportional to temperature which is in milliVolts. Therefore to
drive further stages of system, this signal is amplified using instrumentation amplifier.
 The amplified output is fed to channel 3 of ADC and 8085 provides High to Low SOC and ALE
signal.
 When ADC completes the conversion, 8085 reads the equivalent digital data from Port A which is
the current value of temperature of object.
 This value of measured temperature is then sent to display system.
 For measuring temperature of furnace, water bath, etc. 8085 1st measures current temperature (t1)
and compares with the reference temperature (T1) at which the temperature is to be kept constant.
 If the measure temperature (t1) is greater than reference temperature (T1) then 8085 sends control
signal to the transistorized relay circuit through Port B and turns OFF the heating process to maintain
temperature at desired level.
 If the measure temperature (t1) is less than reference temperature (T1) then 8085 sends control
signal to the transistorized relay circuit through Port B and turns ON the heating process to maintain
temperature at desired level, thus maintaining the temperature of furnace, bath tub, etc.

8259 programmable interrupt controller

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8259 programmable interrupt controller