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8259 Programmable Interrupt Controller
- 2. Introduction Features Pin Diagram Block Diagram Description of blocks
- 3. PIC A special purpose integrated circuit that function as an overall manager in an interrupt driven system. It accepts request from the peripheral equipment,determines which of the incoming request is of the highest priority, ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination. PICs typically have eight interrupt lines, and two PICs are often cascaded to provide 15 available interrupt lines
- 4. 8 levels of interrupts. Can be cascaded in master-slave configuration to handle 64 levels of interrupts. Internal priority resolver. Fixed priority mode and rotating priority mode. Individually maskable interrupts. Modes and masks can be changed dynamically. Accepts IRQ, determines priority, checks whether incoming priority > current level being serviced, issues interrupt signal. In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector number. Polled and vectored mode. Starting address of ISR or vector number is programmable. No clock required.
- 6. D0-D7 Bi-directional, tristated, buffered data lines. Connected to data bus directly or through buffers. RD-bar Active low read control WR-bar Active low write control A0 Address input line, used to select control register. CS-bar Active low chip select CAS0-2 Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC reads slave ID no. from master on these lines. It may be regarded as slave-select. SP-bar / EN-bar Slave program / enable. In non-buffered mode, it is SP-bar input, used to distinguish master/slave PIC. In buffered mode, it is output line used to enable buffers. INT Interrupt line, connected to INTR of microprocessor. INTA-bar Interrupt ack, received active low from microprocessor. IR0-7 Asynchronous IRQ input lines, generated by peripherals.
- 8. This 3- state, bidirectional 8-bit buffer is used to interface the 8259 to the system data bus. Control words and status information are transferred through the data bus buffer.
- 9. The function of this block is to accept OUTPUT commands from the CPU. It contains the initialization command word (ICW) register and operation command word (OCW) register which store the various control formats for device operation. This function block also allows the status of 8159Ato be transferred to the data bus.
- 10. IRR stores all the interrupt inputs that are requesting service. Basically, it keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.
- 11. The IMR is used to disable (Mask) or enable (Unmask) individual interrupt inputs. Each bit in this register corresponds to the interrupt input with the same number. The IMR operation on the IRR. Masking of higher priority input will not affect the interrupt request lines of lower priority. To unmask any interrupt the corresponding bit is set ‘0’.
- 12. The in service registers keeps tracks of which interrupt inputs are currently being serviced. For each input that is currently being serviced the corresponding bit will be set in the in service register. Each of these 3-reg can be read as status reg.
- 13. This logic block determines the priorities of the set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during pulse.
- 14. This function blocks stores and compare the IDS of all 8259’s in the reg. The associated 3-I/O pins (CAS0- CAS2) are outputs when 8259 is used a master. Master and are inputs when 8259 is used as a slave. As a master, the 8259 sends the ID of the interrupting slave device onto the cas2-cas0. The slave thus selected will send its pre-programmed subroutine address on to the data bus during the next one or two successive pulses.