Introduction to embedded computing and arm processors

EC6703 –Embedded and Real Time
Systems
Mr.G.Sivakumar
Ramco Institute of Technology ,
Rajapalayam.

Introduction to
Embedded Computing and
ARM Processors

Introduction to Embedded Computing and
ARM Processors
• Complex systems and microprocessors
• Embedded system design process
• Design example: Model train controller
• Instruction sets preliminaries
• ARM Processor
• CPU: programming input and output
• Supervisor mode, Exceptions and Traps
• Co-processors
• Memory system mechanisms
• CPU performance
• CPU power consumption

Introduction to Embedded Computing
• What is Embedded Systems ???

• What is Embedded Systems ???
– An embedded system is a system that has
embedded software in a computer hardware.
– The system is dedicated for either an
application(s) or specific part of an application
Eg.
– Washing machine
– Cooking machine
– Automative chocolate vending machines
– Multitasking toys

• Three main components of Embedded
Systems ???
– Hardware
– Application Software
– RTOS – Supervises application software and
provides mechanism to the processor run a
process as per scheduling and do context
switching between various processes. It organize
the access of resources for sequence of series
task.

• Components of Embedded System

• Constraints of Embedded Systems ???
– Hardware
– Available System Memory
– Available Processor speed
– Deadlines
– Power Consumption
– Upgradeability

Complex Systems and Microprocessors
• Embedding Computers
• Characteristics of Embedded computing
application
• Why use microprocessors?
• Challenges in embedded computing system
design
• Performance of embedded computing systems

Embedding Computers
• It is any device that includes a programmable
computer but is not itself intended to be a general
purpose computer
• Whirlwind – 1940’s (aircraft simulator) was first
computer support real time operation.
• Levels of Microprocessors based on their word size
(8,16,32 bit )
• Application of Microprocessors (car, washing
machine, Digital television )-High end car contains
more than 100 microprocessors ,low end contains
only 40 processors.

BMW 850i Brake and Stability control system
• ASC +T – it improves car stability during
maneuvering
• ABS – It temporarily release the break on the
wheel when it rotates too slowly.

• Characteristics of Embedded Systems ???
– Complex Algorithms
– User Interface
– Real Time
– Multirate
– Size and Weight
– Manufacturing Cost
– Power and Energy

Why Use Microprocessors?
• Alternatives: field-programmable gate arrays
(FPGAs), custom logic, etc.,
• Microprocessors use much more logic to
implement a function than does custom logic
• Flexible – Easy to design families of products
• Efficient to implement digital system
• It execute programs efficiently
• Programmability
• Real time
• Low power and low cost

Challenges…
• How much hardware need
• How to meet deadlines
• How to minimize power consumption
• How to upgrade
• Does it really work?
– Is the specification correct?
– Does the implementation meet the specification?
– How do we test for real-time characteristics?
– How do we test on real data?
• How do we work on the system?
– Observability, controllability?
– What is our development platform?

Performance in embedded computing :
• Embedded system designers, in contrast, have a very clear
performance goal in mind—their program must meet its deadline.
At the heart of embedded computing is real-time computing,
which is the science and art of programming to deadlines.
• The program receives its input data; the deadline is the time at
which a computation must be finished.
 CPU: The CPU clearly influences the behavior of the program,
particularly when the CPU is a pipelined processor with a cache.
■ Platform: The platform includes the bus and I/O devices. The
platform components that surround the CPU are responsible for
feeding the CPU and can dramatically affect its performance.
■ Program: Programs are very large and the CPU sees only a small
window of the program at a time. We must consider the structure
of the entire program to determine its overall behavior.

■Task: We generally run several programs
simultaneously on a CPU, creating a multitasking
system. The tasks interact with each other in ways
that have profound implications for performance.
■ Multiprocessor: Many embedded systems have more
than one processor—they may include multiple
programmable CPUs as well as accelerators. The
interaction between these processors adds yet more
complexity to the analysis of overall system
performance

Embedded System Design Process

Design methodologies
• It is a procedure for designing a system.
• It allows us to keep a scorecard on a design to
ensure that we have done everything we need
to do.
• It allows us to develop computer-aided design
tools.
• A design methodology makes it much easier
for members of a design team to
communicate.

Embedded System Design Process
Top-down design:
start from most abstract
description;
work to most detailed.
Bottom-up design:
work from small components to
big system.

Requirements
• Plain language description of what the user
wants and expects to get.
• May be developed in several ways:
– talking directly to customers;
– talking to marketing representatives;
– providing prototypes to users for comment.

Requirements
• Functional requirements:
– output as a function of input.
• Non-functional requirements:
– time required to compute output;
– size, weight, etc.;
– power consumption;
– reliability;
– etc.

Requirement Form
name
purpose
inputs
outputs
functions
performance
manufacturing cost
power
physical size/weight

Specification
• It serves as the contract between the customer and the
architects. As such, the specification must be carefully written
so that it accurately reflects the customer’s requirements and
does so in a way that can be clearly followed during design.
• The specification should be understandable enough so that
someone can verify that it meets system requirements and
overall expectations of the customer.

Architecture design
• Architecture is the plan for the overall structure
of the system that will be used later to design the
components that make up the architecture.
• Architecture design must give an idea about
– What major components need for satisfying the
specification?
– What hardware components: like CPUs, peripherals,
etc.
– What Software components
– Must take into account functional and non-functional
specifications.

Designing hardware and software
components
• The component design effort builds those
components to satisfy architecture and
specification.
• The components will in general include both
hardware—FPGAs, boards, and so on and
software modules.
• Some components are ready-made, some can be
modified from existing designs, others must be
designed from scratch( that is new design).

System integration
• System integration is Putting together the components.
– Many bugs appear only at this stage.
• Bugs are typically found during system integration, and good
planning can help us find the bugs quickly.
• System integration is difficult because it usually uncovers
problems. It is often hard to observe in the system, to
determine exactly what is wrong—the debugging facilities for
embedded systems are usually much more limited than what
you.
• Inserting appropriate debugging facilities during design can
help ease system integration problems would find on desktop
systems.

GPS moving map requirements
name GPS moving map
purpose consumer-grade
moving map for driving
inputs power button, two
control buttons
outputs back-lit LCD 400 X 600
functions 5-receiver GPS; three
resolutions; displays
current lat/lon
performance updates screen within
0.25 sec of movement
manufacturing cost $100 cost-of-goods-
sold
power 100 mW
physical size/weight no more than 2: X 6:,
12 oz.
lat: 40 13 lon: 32 19
I-78
ScotchRoad

GPS Specification
• Should include:
– What is received from GPS;
– map data;
– user interface;
– operations required to satisfy user requests;
– background operations needed to keep the
system running.

GPS moving map hardware architecture

GPS moving map software architecture

FORMALISMS FOR SYSTEM DESIGN
• UML – Unified Modeling Language
• UML was designed to be useful at many levels
of abstraction in the design process.
• UML is useful because it encourages design by
successive refinement(removing unwanted
things) and progressively adding detail to the
design, rather than rethinking the design at
each new level of abstraction.

• Many graphical elements in UML diagram
• UML design emphasis on
– Design is described as number of interacting
objects rather than a few large monolithic blocks of
code
– Objects will correspond to real pieces of S/W and
H/W
• The choice of an interface is a very important
decision in object-oriented design.

• Structural Description
• Behavioral Description

A Class in UML notation
Display
pixels
elements
menu_items
mouse_click()
draw_box
operations
class name
Attributes

An object in UML notation
d1: Display
pixels: array[] of pixels
elements
menu_items
object name
class name
attributes

There are several types of relationships that can
exist between objects and classes:
■ Association - occurs between objects that
communicate with each other but have no
ownership relationship between them.
■ Aggregation - describes a complex object made
of smaller objects.
■ Composition - is a type of aggregation in which
the owner does not allow access its objects.
■ Generalization - allows us to define one class in
terms of another.

Class derivation
– Derived class inherits attributes, operations of
base class.
Derived_class
Base_class
UML
generalization

Class derivation example
Display
pixels
elements
menu_items
pixel()
set_pixel()
mouse_click()
draw_box
BW_display Color_map_display
base
class
derived class

Multiple inheritance
Speaker Display
Multimedia_display
base classes
derived class

• A link describes a relationship between
objects;
• Associations capture type information about
these links.

State Machine
a b
state state name
transition
• Describe transition from one state to another state

Types of events
• Signal: asynchronous event.
• Call: synchronized communication.
• Timer: activated by time.

Signal event
<<signal>>
mouse_click
leftorright: button
x, y: position
declaration
a
b
mouse_click(x,y,button)
event description

Call event
c d
draw_box(10,5,3,2,blue)

Time out event
e f
tm(time-value)

Sequence diagram
m: Mouse d1: Display u: Menu
mouse_click(x,y,button)
which_menu(x,y,i)
call_menu(i)
time

Model Train setup
console
power
supply
rcvr motor
header commandaddress
Message
ECC

• The user sends messages to the train with a control box
attached to the tracks. The control box may have controls
such as a throttle (a device controlling the flow of fuel or
power to an engine), emergency stop button, and so on.
• Train receives its electrical power from the two rails( steel bar
or continuous line of bars laid on the ground) of the track, the
control box can send signals to the train over the tracks by
modulating the power supply voltage.
• The control box sends packets over the tracks to the receiver
on the train.
• The train includes analog electronics to receive bits and a
control system to set the train motor’s speed and direction
based on those commands.

• Each packet includes an address, so that the console
can control several trains on the same track; the packet
also includes an error correction code (ECC),to guard
against transmission errors.
• Console can control 8 trains on 1 track.
• Throttle has at least 63 levels.
• Inertia control adjusts responsiveness with at least 8
levels.
• Emergency stop button.

Requirement Form
name Model train controller
purpose Control speed of 8 model trains.
inputs Throttle, inertia, emergency stop,
train number
outputs Train control signals
functions Set engine speed. inertia; emergency
stop
performance Can update train speed at least 10
times/sec
manufacturing cost $50
power 10W (wall powered)
Size/Weight console comfortable for 2 hands

DCC
• Digital Command Control
• National Model Railroad Association
• Defines a way in which model trains, controllers
communicate
• Standard S-9.1, DCC Electrical Standard.
• Standard S-9.2, DCC Communication Standard

DCC Electrical Standard
• The Electrical Standard deals with voltages
and currents on the track.
• Bits are encoded in the time between
transitions, not by voltage levels. A 0 is at least
100 µs while a 1 is nominally 58 µs.
time
logic 1 logic 0
58 µs >= 100 µs

DCC Communication Standard
• Basic packet format: PSA(sD)+E
• P: preamble = 1111111111.
• S: packet start bit = 0.
• A: Address data byte, An address is eight bits long. The
addresses 00000000, 11111110, and 11111111 are reserved.
• s: data byte start bit =0.
• D: data byte (data payload),which includes eight bits. A data
byte may contain an address, instruction, data, or error
correction information.
• E: packet End bit = 1.

DCC Packet Types
• Baseline packet: minimum packet that must
be accepted by all DCC implementations.
– Address data byte gives receiver address.
– Instruction data byte gives basic instruction.
– Error correction data byte gives ECC

Specification
• Conceptual Specification
• Detailed Specification

Conceptual Specification
• Before we create a detailed specification, we
will make an initial, simplified specification.
command name parameters
set-speed speed
(positive/negative)
set-inertia inertia-value (non-
negative)
estop none

Message classes
command
set-inertia
value: unsigned-
integer
set-speed
value: integer
estop

Typical control sequence
:console :receiver
1..n: command

Console system classes
console
panel formatter transmitter
Knob* sender*
1
1
1
11 1
1 1 1 1
• The console needs to perform three functions: read the state of the front
panel on the command unit, format messages, and transmit messages.
• The train receiver must also perform three major functions: receive the
message, interpret the message (taking into account the current speed ,
inertia setting, etc.),and actually control the motor
* = physical object

Console system classes
• Panel: describes analog knobs and interface
hardware.
• Formatter: turns knob settings into bit
streams.
• Transmitter: sends data on track.

Train system classes
train set
train
receiver controller
motor
interface
detector*
pulser*
1
1..t
1
1
1 1
1 1
1
1
1
1

Train class roles
• Receiver: digitizes signal from track.
• Controller: interprets received commands and
makes control decisions.
• Motor interface: generates signals required by
motor.

Detailed Specification
• Refining for more detailed specification
• Not complete specification, but will add detail
to the classes and major decisions in the
specification.

Console physical object classes
knobs*
train-knob: integer
speed-knob: integer
inertia-knob: unsigned-
integer
emergency-stop: boolean
Set-knobs()
sender*
send-bit()

Train Speed Control
• Motor controlled by pulse width modulation:
V
+
-
duty
cycle

Panel and motor interface classes
panel
train-number() : integer
speed() : integer
inertia() : integer
estop() : boolean
new-settings()
motor-interface
speed: integer
panel class defines the controls.
new-settings() behavior reads the controls
motor-interface class defines the motor speed
held as state

Transmitter and receiver classes
transmitter
send-speed(adrs: integer,
speed: integer)
send-inertia(adrs: integer,
val: integer)
set-estop(adrs: integer)
receiver
current: command
new: boolean
read-cmd()
new-cmd() : boolean
rcv-type(msg-type:
command)
rcv-speed(val: integer)
rcv-inertia(val:integer)
Transmitter class has one behavior for each
type of message sent.
 Receiver function provides methods to
 Detect a new message;
 Determine its type;
 Read its parameters (estop has no
parameters).

Control input sequence diagramchangeinspeed/
inertia/estop
changein
trainnumber
:knobs :panel :formatter :transmitter
change in
control
settings
read panel
panel settings
panel-active
send-command
send-speed,
send-inertia.
send-estop
read panel
panel settings
read panel
panel settings
change in
train
number
set-knobs
new-settings

Formatter operate behavior
idle
update-panel()
send-command()
panel-active() new train number
other

Computer Architecture Taxonomy
• Von Neumann / Harvard Architecture
• CISC / RISC
• Little endian / Big endian
• Instruction Set characteristics
– Fixed versus variable length
– Addressing modes
– Number of operands
– Types of operation supported

Processor and Memory organization
• Follows RISC Architecture
• Both in Von Neumann and Harvard Architecture
• 32 bit address line
• Both Little endian and Big endian

Von Neumann and Harvard Architecture
• The memory holds both data and instructions, and can be read or written when
given an address. A computer whose memory holds both data and instructions is known as
a von Neumann machine.
• Harvard machine has separate memories for data and program. The program counter
points to program memory, not data memory. As a result, it is harder to write self-
modifying programs (programs that write data values, then use those values as
instructions) on Harvard machines.
Follows RISC Architecture
Both in Von Neumann and Harvard
Architecture
32 bit address line
Both Little endian and Big endian

Data Operations
• Arithmetic and logical operations in C are performed in
variables. Variables are implemented as memory locations.
• In the ARM processor, arithmetic and logical operations
cannot be performed directly on memory locations. ARM is a
load-store architecture—data operands must first be loaded
into the CPU and then stored back to main memory to save the
results.
• ARM has 16 general-purpose registers, r0 through r15. The
r15 register has the same capabilities as the other registers, but
it is also used as the program counter.

• The other important basic register in the programming model is the
current program status register (CPSR).
• This register is set automatically during every arithmetic, logical, or
shifting operation.
■ The negative (N) bit is set when the result is negative in two’s-
complement arithmetic.
■ The zero (Z) bit is set when every bit of the result is zero.
■ The carry (C) bit is set when there is a carry out of the operation.
■ The overflow(V) bit is set when an arithmetic operation results in an
overflow.
Data Operations…..

Logical Operations
• op Rd, Rm

Compare Instructions
AND operation
XOR operation

Introduction to embedded computing and arm processors

Load-Store Instructions
• LDR r0,[r1]
• LDR r0,[r1-r2]
• LDR r0,[r1, #5]
• ADR r1, FOO

Flow of Control
• The B (branch) instruction is the basic mechanism
in ARM for changing the flow of control.
• The address that is the destination of the branch
is often called the branch target.
• The offset is in words, but because the ARM is
byte addressable, the offset is multiplied by four
(shifted left two bits, actually) to form a byte
address.
• Thus, the instruction
B #400
• will add 400 to the current PC value.

CPU: Programming input and
output

Programming Input and Output
• Input and Output devices
• Input and Output primitives
• Busy-wait I/O
• Interrupts

Input and Output devices
The CPU talks to the device by reading and writing the registers. Devices
typically have several registers:
■ Data registers hold values that are treated as data by the device, such as the
data read or written by a disk.
■ Status registers provide information about the device’s operation, such as
whether the current transaction has completed.

Input and Output primitives
• I/O mapped I/O (IN, OUT inst)
• Memory Mapped I/O (LDA, STA inst)

Busy-wait I/O
The simplest way to communicate with the
device in a program in busy-wait I/O
Asking an I/O device whether it is finished by
reading its status register in often called as
polling

Interrupts
The program that runs when no interrupt is being handled is
often called the foreground program; when the interrupt handler
finishes, it returns to the foreground program, wherever processing
was interrupted.

Interrupts
• Maskable / Non maskable Interrupts
• interrupt priorities: allow the CPU to recognize
some interrupts as more important than others.
• interrupt vectors :allow the interrupting device
to specify its handler.

Interrupt Priorities
• Using polling to share an interrupt over several
devices

Interrupt Vectors
• Priorities
• determine which device is serviced first,and
vectors determine what routine is
• used to service the interrupt.The combination
of the two provides a rich interface
• between hardware and software.
Interrupt Priorities - determine which device is serviced first, and
interrupt vectors - determine what routine is used to service the
interrupt.
The combination of the two provides a rich interface between
hardware and software.

Interrupts in ARM ARM7 supports two types of interrupts:
• Fast interrupt requests(FIQs) and interrupt requests (IRQs)
FIQ takes priority over an IRQ
• The interrupt table is always kept in the bottom memory
addresses,starting at location 0. The entries in the table
typically contain subroutine calls to the appropriate
handler.
The ARM7 performs the following steps when responding to
an interrupt
■ saves the appropriate value of the PC to be used to return,
■ copies the CPSR into a saved program status register (SPSR),
■ forces bits in the CPSR to note the interrupt, and
■ forces the PC to the appropriate interrupt vector.
When leaving the interrupt handler, the handler should:
■ restore the proper PC value,
■ restore the CPSR from the SPSR, and
■ clear interrupt disable flags.

Supervisor mode, Exceptions and
Traps

Supervisor Mode
• Supervisor mode have more privileges than user
mode
SWI CODE_1
• It causes the CPU to go into supervisor mode
• It allows the program to request various services
from the supervisor mode
• The old value of CPSR is stored to SPSR.
• SPSR of supervisor mode is referred to as SSR_svc
• To return from supervisor mode, PC is restored
form r14 and CPSR is restored from SPSR_svc

Supervisor Mode
• The various functions of ARM processor in
supervisor modes are:
– Exception
– Prioritization
– Vectoring
– Traps.

Exception
• An exception is a internally detected error
– Division by zero
• The exception mechanism provides a way for the
program to react to such unexpected events
– Resets, undefined instructions, illegal memory
accesses

Traps
• It is an software interrupt
• It is an exception generated by an instruction.
• It enters in to supervisor mode.
• ARM uses SWI instruction for traps.

Co-processors
• A coprocessor is a special set of circuits in a
microprocessor chip that is designed to
manipulate numbers or perform some other
specialized function more quickly than the basic
microprocessor circuits could perform the same
task.
• A coprocessor offloads specialized processing
operations, thereby reducing the burden on the
basic microprocessor circuitry and allowing it to
work at optimum speed.
• It allows flexibility in instruction set level.
• Ex, floating point operations

Co-processors
• In ARM some instructions are reserved for
coprocessor
• Coprocessor is tightly coupled with CPU
• If coprocessor is not present, and if CPU
receives coprocessor instruction, then illegal
instructions traps are used to handle these
situations
• 16 co-processors are supported by ARM
architecture

• A cache controller mediates between the CPU and the main
memory. The cache controller sends a memory request to the
cache and main memory.
• If the requested location is in the cache, the cache controller
forwards the location’s contents to the CPU and aborts the
main memory request; this condition is known as a cache hit.
• If the location is not in the cache, the controller waits for the
value from main memory and forwards it to the CPU; this
situation is known as a cache miss.

Caches
• Catch miss are several types :
– Compulsory miss (cold miss) : occurs the first time
a location is used
– Capacity miss : is caused by a too large working
set
– Conflict miss: happens when two location map to
the same location in the cache
tav = htcahce + (1-h)tmain

Two level Cache system
tav = h1tL1 + (h2-h1) tL2 +(1-h2)tmain

Direct mapped cache
The cache consists of cache blocks, each of which includes a
tag to show which memory location is represented by this block, a
data field holding the contents of that memory, and a valid tag to show
whether the contents of this cache block are valid.

• An address is divided into three sections. The index is used to
select which cache block to check.
• The tag is compared against the tag value in the block
selected by the index. If the address tag matches the tag value
in the block, that block includes the desired memory location.
• If the length of the data field is longer than the minimum
addressable unit, then the lowest bits of the address are used
as an offset to select the required value from the data field.

 Writing is more complicated than reading
Write-through
• Every write changes both the cache and the corresponding
main memory location (usually through a write buffer). This
scheme ensures that the cache and main memory are
consistent, but may generate some additional main memory
traffic.

Set Associative cache
• A set-associative cache is characterized by the number of banks.A set is
formed by all the blocks that share the same index.
• Each set is implemented with a direct-mapped cache. A cache request is
broadcast to all banks simultaneously. If any of the sets has the location, the
cache reports a hit

Set associative cache generally provides
higher hit rates than the direct mapped cache
because conflicts between a small set of
locations can be resolved with in the cache

Memory management unit and address
translation
• A MMU translates addresses between the CPU and physical memory. This
translation process is often known as memory mapping since addresses are
mapped from a logical space into a physical space.
• MMUs allowed software to manage multiple programs in a single physical
memory.
• MMU accepts logical addresses from the CPU. Logical addresses refer to the
program’s abstract address space but do not correspond to actual RAM
locations.The MMU translates them from tables to physical addresses that do
correspond to RAM.

• In a virtual memory system, the MMU keeps track of
which logical addresses are actually resident in main
memory; those that do not reside in main memory
are kept on the secondary storage device.
• When the CPU requests an address that is not in
main memory, the MMU generates an exception
called a page fault.
• The handler for this exception executes code that
reads the requested location from the secondary
storage device into main memory.

• There are two styles of address translation: segmented and
paged. Each has advantages and the two can be combined to
form a segmented paged addressing scheme.
• Segmenting is designed to support a large, arbitrarily sized
region of memory, while pages describe small, equally sized
regions.
• A segment is usually described by its start address and size,
allowing different segments to be of different sizes. Pages are
of uniform size, which simplifies the hardware required for
address translation.

Address translation for a segment
• The MMU would maintain a segment register that describes the currently
active segment.(Current segment)
• The address extracted from an instruction would be used as the offset for the
address
• The physical address is formed by adding the segment base to the offset

Address translation for a page
• In this ,logical address is divided into two sections, including a page number
and an offset. The page number is used as an index into a page table, which
stores the physical address for the start of each page.
• The MMU simply needs to concatenate the top bits of the page starting
address with the bottom bits from the page offset to form the physical
address.

• The page table may be organized in several ways, The simplest scheme is a flat
table. The table is indexed by the page number and each entry holds the page
descriptor. A more sophisticated method is a tree. The root entry of the tree holds
pointers to pointer tables at the next level of the tree; each pointer table is
indexed by a part of the page number.

ARM two stage address translation
• The efficiency of paged address translation may be increased by caching page
translation information. A cache for address translation is known as a translation
lookaside buffer (TLB).
• The MMU reads the TLB to check whether a page number is currently in the
TLB cache and, if so, uses that value rather than reading from memory.

CPU Performance
• Pipelining
• Cache performance

Pipelining
Modern CPUs are designed as pipelined machines in which several
instructions are executed in parallel. Pipelining greatly increases the efficiency of
the CPU.
 Fetch the instruction is fetched from memory.
 Decode the instruction’s opcode and operands are decoded to determine
what function to perform.
 Execute the decoded instruction is executed.

Pipelining
• In load multiple (LDMIA) instruction, there are two registers to load, the
instruction must stay in the execution phase for two cycles.
• In a multiphase execution, the decode stage is also occupied, since it must
continue to remember the decoded instruction.
• As a result, the SUB instruction is fetched at the normal time but not decoded
until the LDMIA is finishing.

Pipelining
Branches also introduce control stall delays into the pipeline, commonly referred to as
the branch penalty.

Cache Performance
• Cache Hit
• Cache Miss
– Compulsory Miss
– Conflict Miss
– Capacity Miss

CPU Power Consumption
• Power Supply Voltage
– CPU can be used at reduced voltage levels
• Capacitive toggling
– CPU can be operated at a lower clock frequency
– Eliminating unnecessary changes to the inputs
• Leakage
• CPU may internally disable certain function units that
are not required for currently executing function
• CPU may allow parts of the CPU to be totally
disconnected from the power supply to eliminate
leakage currents.

CPU Power Consumption
• Two Types of power management features
– Static Power Management
– Dynamic Power Management
• Static power management
• Power down mode
• Dynamic power management
• CPU may turnoff certain sections of the CPU when the
instructions being executed do not need them

Introduction to Embedded Computing and
ARM Processors
• Complex systems and microprocessors
• Embedded system design process (GPS)
• Design example: Model train controller
• Instruction sets preliminaries
• ARM Processor
• CPU: programming input and output
• Supervisor mode, Exceptions and Traps
• Co-processors
• Memory system mechanisms
• CPU performance
• CPU power consumption

Reference :
• Marilyn Wolf, “Computers as Components - Principles of
Embedded Computing System Design”, Third Edition
“Morgan Kaufmann Publisher (An imprint from Elsevier),
2012.
• David. E. Simon, “An Embedded Software Primer”, 1st
Edition, Fifth Impression, Addison-Wesley Professional, 2007.

Introduction to embedded computing and arm processors

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