Fault detection and test minimization methods
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This document summarizes and compares different fault detection and test minimization methods for combinational circuits. It discusses traditional methods like fault table, path sensitizing, and Boolean difference approaches. It also covers more recent heuristic and genetic algorithm methods. The conclusion states that iterative methods provide optimal solutions for circuits of varying complexity, while traditional methods require constructing large fault tables. The document aims to survey fault detection and test minimization techniques for combinational logic.
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Fault detection and test minimization methods
- 1. Fault Detection and Test Minimization Methods for Combinational Circuits PRAVEEN KAUNDAL SID-15215015
- 2. Abstract Rapid increase in population increased the usage of digital components dramatically and their production. For profitable income, the cost of the finished product and time taken for marketing the product needs to be reduced. In this paper, the authors conducted extensive survey of methods developed earlier to detect faults and minimize test set in digital circuits. The survey is limited to methods for simple combinational circuits only. In effect, this paper compares different fault detection and test minimization methods for simple circuits.
- 3. INTRODUCTION In recent years, the development of integrated circuit technology has accelerated rapidly. The digital systems are built with more and more complexity, the fault testing and diagnosis of digital circuits becomes an important and indispensable part of the manufacturing process. As the device complexity increases, testing becomes even more complex. As the system complexity increases and time-to-market decreases.
- 4. This results in increased test time and higher test cost. At the same time, the manufacturing cost of a device is reduced due to the higher levels of integration. Hence the necessity of reducing the test cost. To decrease the test cost, the time required to test a device needs to be decreased. So, we simply need to devise a test set that is small in size.
- 5. FAULT DETECTION AND TEST MINIMIZATION METHODS Minimizing test sets is simply termed as test set compaction. Most commonly used method is fault table method and number of other basic analytic method.
- 6. Fixed Scheduled Test Minimization Method If x1, x2,…..,xn are the input variables to a single output circuit whose fault-free (correct) output is z = z(x1,…..xn).f1,f2,…..fi are the erroneous outputs, each corresponding to one of the possible faults f1,f2,….fi. Each corresponding faulty and fault-free outputs are compared using Exclusive-OR operation results zf1,zf2…zfi single bit erroneous outputs fault detection.
- 7. Heuristic Method In this method, fault table alone is created. A diagnosing tree is created by divide the fault diagnostic matrix into two sub matrices based on essential test number. Left subtree contains fault free output column numbers from the matrix(0s) and right subtree contains faulty output column numbers from the matrix(1s). The process is repeated until both left and right children results in a single column number in them.Essential test set is found after removing redundant test numbers in nodes.
- 8. Path Sensitizing Method This is one of the earliest method used for fault detection. In this method fault detection test may be found by examining the paths of transmission from the location of an assumed fault to one of its primary outputs.
- 9. Equivalent-Normal-Form Method The Equivalent Normal Form(ENF) of a circuit is obtained by expressing the output of each gate as a sum-of-products expression of its inputs and preserving the identity of each gate by a suitable subscript.
- 10. Two- Level- Circuit FD Method The previous methods of construction of a complete fault-detection test set for a combinational circuit using the two basic approaches. First approach is to examine each “individual fault. Second approach is to examine each “path”. A third approach to the problem is instead of examining each individual fault or each path, it is proposed to examine each gate of the circuit. A very simple and direct method for constructing a minimal complete fault-detection.
- 11. Boolean Difference Method It is simple and straight forward ways of deriving test sequences for combinational circuits. Boolean difference is defined as being the exclusive-or operation between two boolean functions, one representing the normal circuit and other representing the faulty circuit. Thus if the Boolean difference is a 1, a fault is indicated. Assume that there is a switching function that has one output F and n inputs x1,x2,….xn, so F(X) = F(x1,x2,….,xn ). If one of the inputs to the switching function was in error, say input xi , then the output would be F(x1,…..,x’i,……,xn).To analyze the action of the circuit when an error occurs, it is desirable to know under what circumstances the two outputs are the same.
- 12. Genetic Algorithm Method The two methods Fixed Scheduled Fault Detection and Heuristic test minimization adapted for test minimization requires very large fault table to be constructed. Genetic Algorithm approach proposed in this work overcomes the problem of creating a very large fault table. Test numbers are chosen at random and evolutionary strategy is used for improving the solution.
- 13. CONCLUSION In this paper, the authors surveyed the methods for fault detection and test minimization in two stage combinational circuits. Different methods that range from very basic methods to the recent fast evolutionary(genetic) methods are studied. Merits and demerits of those methods are presented. Iterative methods yield optimal solutions for circuits of various complexity.
- 14. REFERENCES • Alok Shreekant Doshi, “Independence Fault Collapsing and Concurrent Test Generation”, May 11, 2006. • S. B. Akers, "On a theory of Boolean functions, " J. SIA M, vol.7, • V. Amar and N. Condulmari, "Diagnosis of large combinational networks," IEEE Trans. Electronic Computers, vol. EC-16, pp. 675-680, October 1967