ASIC-DESIGN.pdf machne language explanation

’14EC770 : ASIC DESIGN’
An Introduction
Application - Specific
Integrated Circuit
Dr.K.Kalyani
AP, ECE,
TCE. 1

VLSI COMPANIES IN INDIA
• Motorola India – IC design center
• Texas Instruments – IC design center in Bangalore
• VLSI India – ASIC design and FPGA services
• VLSI Software – Design of electronic design automation tools
• Microchip Technology – Offers VLSI CMOS semiconductor components for embedded
systems
• Delsoft – Electronic design automation, digital video technology and VLSI design
services
• Horizon Semiconductors – ASIC, VLSI and IC design training
• Bit Mapper – Design, development & training
• Calorex Institute of Technology – Courses in VLSI chip design, DSP and Verilog HDL
• ControlNet India – VLSI design, network monitoring products and services
• E Infochips – ASIC chip design, embedded systems and software development
• EDAIndia – Resource on VLSI design centres and tutorials
• Cypress Semiconductor – US semiconductor major Cypress has set up a VLSI
development center in Bangalore
• VDAT 2000 – Info on VLSI design and test workshops
2

VLSI COMPANIES IN INDIA
• Sandeepani – VLSI design training courses
• Sanyo LSI Technology – Semiconductor design centre of Sanyo Electronics
• Semiconductor Complex – Manufacturer of microelectronics equipment like
VLSIs & VLSI based systems & sub systems
• Sequence Design – Provider of electronic design automation tools
• Trident Techlabs – Power systems analysis software and electrical machine
design services
• VEDA IIT – Offers courses & training in VLSI design & development
• Zensonet Technologies – VLSI IC design firm eg3.com – Useful links for the
design engineer
• Analog Devices India Product Development Center – Designs DSPs in Bangalore
• CG-CoreEl Programmable Solutions – Design services in telecommunications,
networking and DSP
3

Physical Design, CAD Tools.
• SiCore Systems Pvt. Ltd. 161, Greams Road, ...
• Silicon Automation Systems (India) Pvt. Ltd. ( SASI) ...
• Tata Elxsi Ltd. VLSI Design Group, ...
• Tata Infotech Ltd. Bangalore. ...
• Texas Instruments (India) Ltd. Golf View Homes, ...
• TranSwitch (India) Pvt. Ltd. ...
• Vedatech India (Software) Pvt. Ltd.
4

14EC770 : ASIC DESIGN
• Preamble
• 14EC270 : Digital Logic Circuit Design
• 14EC520 : Digital CMOS Systems
• Objective
This course provide the students, the knowledge about
– Physical design flow of IC
• Floor-planning, Placement and Routing
– Experiments explore complete digital design flow of
programmable ASIC through VLSI EDA tools.
– Students work from design entry using verilog code to GDSII file
generation of an ASIC.
5

Course Outcomes
CO1 Describe the design flow, types and the programming
technologies of an ASIC and its construction.
Understand
CO2 Describe the goals, objectives, measurements and
algorithms of partitioning then apply those algorithms to
partition the network to meet the objectives.
Apply
algorithms of floorplanning & placement then apply those
algorithms to place the logic cells inside the flexible blocks
of an ASIC to meet the objectives.
Apply
algorithms of routing then apply those algorithms to route
the channels then describing various circuit extraction
formats and Investigate the issues and discover solutions in
each step of physical design flow of an ASIC.
Analyze
CO5 Design an ASIC for digital circuits with ASIC design flow
steps consists of simulation, synthesis, floorplanning,
placement, routing, circuit extraction and generate GDSII
File for fabrication of an ASIC, then analyze the ASIC to
meet the performance in terms of area, speed and power
using EDA tools.
Analyze
7

Assessment Pattern
Bloom’s
Category
Continuous Assessment Tests Terminal
Examination
1 2 3
Remember 20 0 Practical 0
Understand 50 20 20
Apply 30 30 30
Analyse 0 50 50
Evaluate 0 0 0
Create 0 0 0
8

Integrated Circuit
 Wafer : A circular piece of pure silicon (10-15 cm in dia, but
wafers of 30 cm dia are expected soon)
 Wafer Lot: 5 ~ 30 wafers, each containing hundreds of
chips(dies) depending upon size of the die
 Die: A rectangular piece of silicon that contains one
IC design
 Mask Layers: Each IC is manufactured with successive
mask layers(10 – 15 layers)
 First half-dozen or so layers define transistors
 Other half-dozen define Interconnect
9

Integrated Circuit (IC) in a package
(a) A pin-grid array (PGA) package.
(b) The silicon die or chip is under the package lid.
10

Evolution of IC
• SSI (Small-Scale Integration)-(1962)
– Tens of Transistors
– NAND, NOR
• MSI (Medium-Scale Integration)-(late 1960)
– Hundreds of Transistors
– Counters
• LSI (Large-Scale Integration)-(mid 1970)
– Tens of Thousands of Transistors
– First Microprocessor
• VLSI (Very Large-Scale Integration)-(1980)
– started Hundreds of Thousands of Transistors-several billion transistors in 2009
– 64 bit Microprocessor with cache memory and floating-point arithmetic units
• ULSI (Ultra Large-Scale Integration)-(late 1980)
– More than about one million circuit elements on a single chip.
– The Intel 486 and Pentium microprocessors, use ULSI technology
11

IC technologies
• Bipolar
– More accuracy
• MOS
– Gate-Aluminium
– Low power consumption
– Low cost
• CMOS
– Gate-Poly-Silicon
– Low power consumption
– Low cost
• BiCMOS 12

• Standard ICs
• Glue Logic-Microelectronic system design then
becomes a matter of defining the functions that
you can implement using standard ICs and then
implementing the remaining logic functions
(sometimes called glue logic ) with one or more
custom ICs.
• ASIC
• ASSP (Application-Specific Standard Products)
Types of IC
13

ASIC and Non ASIC
• Examples of ICs that are not ASICs include standard parts such as:
– memory chips sold as a commodity item—ROMs, DRAM, and SRAM;
microprocessors;
– TTL or TTL-equivalent ICs at SSI, MSI, and LSI levels.
• Examples of ICs that are ASICs include:
– a chip for a toy bear that talks;
– a chip for a satellite;
– a chip designed to handle the interface between memory and a
microprocessor for a workstation CPU;
– a chip containing a microprocessor as a cell together with other logic.
• ASSP (two ICs that might or might not be considered ASICs )
– controller chip for a PC and a chip for a modem.
– Both of these examples are specific to an application (shades of an ASIC)
but are sold to many different system vendors (shades of a standard part).
ASICs such as these are sometimes called application-specific standard
products ( ASSPs ).
14

Measurement of IC
• Gate Equivalent
– Number of gates or transistors
– Gate refer to two input NAND Gate
– In CMOS, each NAND gate consist of 4 transistors
– Example : 10k gate IC
– (10,000 two-input NAND gates or 40,000 transistors in
CMOS)
• Feature Size (smallest feature size = )
– Half of smallest transistor length
– Example: 0.5µm IC
– Feature size, = 0.25µm

 15

Types of ASICs – Cont’d
• Full-Custom ASICs: Possibly all logic cells and all mask layers customized
• Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
16

Full-Custom ASICs
 Include some (possibly all) customized logic cells
 Have all their mask layers customized
Manufacturing lead time is typically 8 weeks (time taken to make the IC
does not include design time)
 Full-custom ASIC design makes sense only
 When no suitable existing libraries exist or
 Existing library cells are not fast enough or
 The available pre-designed/pre-tested cells consume too much power
that a design can allow or
 The available logic cells are not compact enough to fit or
 ASIC technology is new or/and so special that no cell library exits.
17

Full-Custom ASICs
 Advantages:
Offer highest performance
lowest cost (smallest die size)
Disadvantages
Increased design time
Increased Complexity
 Higher design cost
 Higher risk.
 Some Examples:
Microporcessor,
High-Voltage Automobile Control Chips
 Ana-Digi Communication Chips
 Sensors and Actuators
18

 Semi-Custom ASICs
 Standard-Cell based ASICs (CBIC- ―sea-bick‖)
 Use predesigned logic cells (Called standard cells) from
standard cell libraries
other mega-cells (Microcontroller or Microprocessors)
full-custom blocks
System-Level Macros(SLMs)
 Functional Standard Blocks (FSBs)
 cores etc
 Get all mask layers customized- transistors and interconnect
 Manufacturing lead time is about 8 weeks
Custom blocks can be embedded
19

 Semi-Custom ASICs – Cont’d
 Standard-Cell based ASICs
(CBIC- ―sea-bick‖) – Cont’d
20

 Standard Cell in Flexible block of CBIC
• Std cell in library is constructed using full-custom design
methodology-
– Same performance and flexibility but reduce time and risk.
• ASIC designer defines only placement of standard cells
– It can be placed anywhere on silicon.
 Construction of Flexible blocks in CBIC
– Standard cells are designed like bricks in a wall.
– Groups of standard cells fit horizontally to form rows.
– The rows stack vertically to form flexible blocks- reshape during design
– Flexible blocks connected with other std cell blocks or full custom block
21

 Wiring cells in Standard Cell based ASICs
•Spacer cells
•The width of each row of standard cells is adjusted so that they may be aligned
using spacer cells .
•Row end cells
•The power buses, or rails, are then connected to additional vertical power rails
using row-end cells at the aligned ends of each standard-cell block.
• Power cells
•If the rows of standard cells are long, then vertical power rails can also be run in
metal2 through the cell rows using special power cells that just connect to VDD
and GND.
•Usually the designer manually controls the number and width of the vertical
power rails connected to the standard-cell blocks during physical design.
•Feedthrough cell:
•Piece of metal that is used to pass a signal through a cell or to a space in a cell waiting
to be used as a feedthrough
22

 Advantages of CBIC
– Save time, money, reduce risk
– Standard cell optimized individually for speed or area
 Disadvantages of CBIC:
– Time to design standard cell library
– Expenses of designing std cell library
– Time needed to fabricate all layers of the ASIC for new design
23

 Gate Array based ASICs
Transistors are predefined on the silicon wafer
Predefined pattern of transistors on a gate array is base array.
Smallest element repeated to form base array is base cell.
Only the top few layers of metal, which define the interconnect between
transistors, are defined by the designer using custom masks.It is often called a
masked gate array ( MGA ).
Less turnaroundtime: fewdays or couple of weeks.
Similar to CBIC –but here space is fixed
24

 Chanelless Gate Array ASIC
•The key difference between a channelless gate array and channeled
gate array
•there are no predefined areas set aside for routing between cells on
a channelless gate array.
•Use an area of transistors for routing in a channelless array, we do
not make any contacts to the devices lying underneath; we simply
leave the transistors unused.
•The logic density—the amount of logic that can be implemented
in a given silicon area is higher for channelless gate array
25

 Difference between Channeled and Chanelless Gate Array ASIC
•contact mask is customized in a channelless gate array,
but is not usually customized in a channeled gate array. This
leads to denser cells in the channelless architectures.
•Customizing the contact layer in a channelless gate array
allows us to increase the density of gate-array cells because
we can route over the top of unused contact sites.
26

 Structured Gate Array based ASICs
- Cont’d
•An embedded gate array or structured gate array (also known as masterslice or
masterimage ) combines some of the features of CBICs and MGAs.
•One of the disadvantages of the MGA is the fixed gate-array base cell. This
makes the implementation of memory, for example, difficult and inefficient.
• In an embedded gate array we set aside some of the IC area and dedicate it to
a specific function.
• This embedded area either can contain a different base cell that is more
suitable for building memory cells, or it can contain a complete circuit block,
such as a microcontroller.
27

Channelled gate array
Adv: Specific space for interconnection
Disadv: compared to CBIC space is not adjustable
Channelless gate array
Adv :
• Logic density is higher for channelless gate array
• Contact layers are customized
Disadv:
• No specific area for routing
• Rows of transistors used for routing are not used for other purpose.
Structured Gate Array
Adv:
• Embedded gate array set in some of IC area and dedicate to specific
function-customized.
• Increase area efficiency, performance of CBIC
• low cost and fast turn around of MGA
Disadv:
Embedded function is fixed
28

 Programmable ASICs
 PLDs - PLDs are low-density devices
which contain 1k – 10 k gates and are
available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs -
FPGAs combine architecture of gate arrays
with programmability of PLDs.
User Configurable
 Contain Regular Structures -
circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming
Technologies
 Allow both Matrix and Row-
based Architectures
29

Programmable Logic Devices
• Programmable logic devices ( PLDs ) are standard ICs
– Available in standard configurations
– Sold in very high volume to many different customers.
– PLDs may be configured or programmed to create a part customized to a specific
application
– PLDs use different technologies to allow programming of the device.
• The important features of PLDs:
– No customized mask layers or logic cells
– Fast design turnaround
• Structure of programmable logic device (PLD)
– A single large block of programmable interconnect
– A matrix of logic macrocells that usually consist of programmable array logic
followed by a flip-flop or latch
30

Examples of PLD
• The simplest type of programmable IC is a read-only memory ( ROM ).
• The most common types of ROM use a metal fuse that can be blown
permanently
(a programmable ROM or PROM ).
• An eraseable programmable ROM (EPROM) , uses programmable MOS
transistors whose characteristics are altered by applying a high voltage.
• Erasable PROM
– Erase an EPROM either by using another high voltage (an electrically erasable
PROM , or EEPROM )
– Exposing the device to ultraviolet light ( UV-erasable PROM , or UVPROM ).
• There is another type of ROM that can be placed on any ASIC—a
maskprogrammable ROM (mask-programmed ROM or masked ROM).
– A masked ROM is a regular array of transistors permanently programmed using
custom mask patterns.
• An embedded masked ROM is thus a large, specialized, logic cell.
31

PROM
PROM, it is not fast enough.
Occupies more space.
32

Type of PLDs-PLA and PAL
• Place a logic array as a cell on a custom
ASIC. This type of logic array is called a
programmable logic array (PLA).
• A PLA has a programmable AND logic
array, or AND plane , followed by a
programmable OR logic array, or OR
plane
• A PAL has a programmable AND plane
and, in contrast to a PLA, a fixed OR
plane.
• Depending on how the PLD is
programmed, we can have an
– Erasable PLD (EPLD),
– Mask-programmed PLD (called as
masked PLD but usually just PLD).
• The first bipolar based PALs, PLAs, and
PLDs used programmable fuses or links.
• CMOS PLDs usually employ floating-gate
transistors
34

Programmable Logic Devices
PLA PLA Design Example
35

PAL
• Suitable to implement
sequential logic.
• Very fast.
36

 Programmable ASICs
 PLDs - PLDs are low-density devices
which contain 1k – 10 k gates and are
available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs -
FPGAs combine architecture of gate arrays
with programmability of PLDs.
User Configurable
 Contain Regular Structures -
circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming
Technologies
 Allow both Matrix and Row-
based Architectures
37

 Programmable ASICs - Cont’d
 Structure of a CPLD / FPGA
38

Essential characteristics of FPGA
• Core-regular array of Programmable basic logic cells implement
combinational or sequential logic
• Matrix of programmable interconnects surround the basic logic cells
• Programmable I/O cells surround the core
• A method of programming the basic logic cells and interconnect
• None of the mask layers are customized
• Design turnaround is few hours.
• Difference between PLD and FPGA:
– FPGA are larger and more complex than PLD
39

Why FPGA-based ASIC Design?
 Choice is based on Many
Factors ;
 Speed
 Gate Density
 Development Time
 Prototyping and Simulation
Time
 Manufacturing Lead Time
 Future Modifications
 Inventory Risk
 Cost
Very Effective Adequate Poor
Requirement FPGA/FPLD Discrete Logic Custom Logic
Speed
Gate Density
Cost
Development Time
Prototyping and Sim.
Manufacturing
Future Modification
Inventory
Development Tools
40

Different Categorizations of FPGAs
 Based on Functional Unit/Logic
Cell Structure
 Transistor Pairs
 Basic Logic Gates: NAND/NOR
 MUX
 Look –up Tables (LUT)
 Wide-Fan-In AND-OR Gates
 Programming Technology
 Anti-Fuse Technology
 SRAM Technology
 EPROM Technology
 Gate Density
 Chip Architecture (Routing Style)
41

Different Types of Logic Cells
42

Different Types of Logic Cells – Cont’d
 Actel Act Logic Module Structure
The Actel ACT 2 and ACT 3 Logic Modules. (a) The C-
Module for combinational logic. (b) The ACT 2 S-Module.
(c) The ACT 3 S-Module. (d) The equivalent circuit
(without buffering) of the SE (sequential element). (e) The
sequential element configured as a positive-edge–triggered
D flip-flop. (Source: Actel.)
 Use Antifuse Programming Tech.
 Based on Channeled GA Architecture
 Logic Cell is MUX which can be configured as multi-input logic gates
43

 Xilinx XC4000 CLB Structure
44

 Altera Flex / Max Logic
Element Structure
Flex 8k/10k Devices – SRAM Based LUTs, Logic
Elements (LEs) are similar to those used in XC5200
FPGA
The Altera MAX architecture. (a) Organization of logic and
interconnect. (b) A MAX family LAB (Logic Array Block).
(c) A MAX family macrocell. The macrocell details vary
between the MAX families—the functions shown here are
closest to those of the MAX 9000 family
45

To SUMMARIZE, FPGAs from various
vendors differ in their
 Architecture (Row Based or Matrix
Based Routing Mechanism)
 Gate Density (Cap. In Equiv. 2- Input
NAND Gates)
 Basic Cell Structure
 Programming Technology
46

Programming Technologies
 Three Programming Technologies
The Antifuse Technology
Static RAM Technology
EPROM and EEPROM Technology
47

Antifuse
[a]
[c]
[b]
[d]
[a]
[a]
[c]
[c]
[b]
[d]
[b]
[b]
[d]
[d]
48

Programming Technologies – Cont’d
 The Antifuse Technology
Invented at Stanford and developed
by Actel
Opposite to regular fuse Technology
Normally an open circuit until a
programming current (about 5 mA) is
forced through it
Two Types:
Actel’s PLICE
[[Programmable Low-Impedance Circuit
Element]-
A High-Resistance Poly-Diffusion
Antifuse
ONO layer offers high resistance
For 5mA, resistance is 500Ω
Programming time-5-10 Minutes
Disadvantages:
It doesn’t allow large amount of
current
Need extra space to connect witnh
metal layer- add parasitic
capacitance.-Unwanted Long Delay.
OTP
[A] Actel Antifuse cross section
[b] Link in Actel Antifuse
[c] Actel Antifuse in metal contacts
[d] Actel Antifuse Resistance
49

QuickLogic’s Low-Resistance
metal-metal antifuse [ViaLink]
technology
Direct metal-2-metal
connections
Higher programming currents
reduce antifuse resistance
For 15mA, resistance is 80 Ω
Advantage:
No parasitic capacitance-
reduce delay
Disadvantages of Antifuse
technology:
Unwanted RC Delay
OTP Technology
Less reliable- electromigration
Need separate programming box-
Activator.
[A] QuickLogic Antifuse – two level
metal
[b] QuickLogic Antifuse – three level
metal
[c] QuickLogic Antifuse in metal contacts
[d] QL Antifuse Resistance
50

 Static RAM Technology
 SRAM cells are used for
As Look-Up Tables (LUT) to
implement logic (as Truth Tables)
As embedded RAM blocks (for
buffer storage etc.)
Two cross coupled inverters and a
standard CMOS process
The configuration cell make or break
connection
As control to routing and
configuration switches
 Advantages
Allows In-System Programming
(ISP)
Suitable for Reconfigurable HW
 Disadvantages
Volatile – needs power all the time /
use PROM to download configuration
data
Larger in size than Antifuse
51

 EPROM and EEPROM Technology-(Altera & Xilinx)
.
 EPROM Cell is almost as small as Antifuse
 Floating-Gate Avalanche MOS (FAMOS) Tech.
Under normal voltage, transistor is on
With Programming Voltage applied, we can turn it off (configuration) to
implement our logic
Exposure to UV lamp (one hour) we can erase the programming
Use EEPROM for quick reconfiguration, also, ISP possible
52

 Summary Sheet
53

ASIC Design Process
S-1 Design Entry: Schematic entry
or HDL description
S-2: Logic Synthesis: Using
Verilog HDL or VHDL and
Synthesis tool, produce a netlist-
logic cells and their interconnect
detail
S-3 System Partitioning: Divide a
large system into ASIC sized pieces
S-4 Pre-Layout Simulation: Check
design functionality
S-5 Floorplanning: Arrange netlist
blocks on the chip
S-6 Placement: Fix cell locations in
a block
S-7 Routing: Make the cell and
block interconnections
S-8 Extraction: Measure the
interconnect R/C cost
S-9 Post-Layout Simulation
54

ASIC Design Flow
1.Design entry. Enter the design into an ASIC design system, either
using a hardware description language ( HDL ) or
schematic entry .
2. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis
tool to produce a netlist —a description of the logic
cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and blocks.
8. Extraction. Determine the resistance and capacitance of the
interconnect.
9. Postlayout simulation. Check to see the design still works with the added loads
of the interconnect.
Steps 1–4 are part of logical design , and steps 5–9 are part of physical design .
• There is some overlap. For example, system partitioning might be considered as either logical or
physical design. To put it another way, when we are performing system partitioning we have to
consider both logical and physical factors.
55

ASIC Design Process – Cont’d
 Altera FPGA Design Flow – A Self-Contained System that does all
from Design Entry, Simulation, Synthesis, and Programming of Altera Devices
56
•EDIF-Electronic Design Interchange
Format
•SDF-Standard Delay Format

ASIC Design Process – Cont’d
 Xilinx FPGA Design Flow – Allows Third-Party Design Entry SW,
Accepts their generated netlist file as an input
57
•XNF-Xilinx Netlist
Format
•LCF-Library Container
File

ASIC-DESIGN.pdf machne language explanation

FPGA Vs ASIC Design Flow
•ECO-
Engineei
rngchan
ge order

Start
RTL Coding
(Using gedit)
Specifications
FunctionalVerification
(Using simvision)
Synthesis
Timing Simulation
DFT (Design For
Testability)
Incisive Tool
Platform
(NCLAUNC
H)
Encounter
RTL
Complier
ASIC Design Flow Using Cadence Tool

Floorplanning
Placement
ClockTree
Synthesis(CTS)
Routing
DRC/LVS
XRC
Power Planning
Encounter RTL
to GDSII
GDSII
GDS-- Graphical
Data Stream
Information
Interchange

UNIT I & II
ASIC Construction &
System Partitioning
Dr.K.Kalyani
AP, ECE,
TCE
•62

Physical Design Steps
• Part of an ASIC design flow showing
the system partitioning, floorplanning,
placement, and routing steps.
• Performed in a slightly different order,
iterated or omitted depending on the
type and size of the system and its
ASICs.
• Floorplanning assumes an increasingly
important role.
• Sequential-Each of the steps shown in
the figure must be performed and each
depends on the previous step.
• Parallel- However, the trend is
toward completing these steps in a
parallel fashion and iterating,
rather than in a sequential manner.
•63

CAD Tools
System partitioning:
• Goal. Partition a system into a number of ASICs.
• Objectives.
– Minimize the number of external connections between the ASICs.
– Keep each ASIC smaller than a maximum size.
Floor planning:
• Goal. Calculate the sizes of all the blocks and assign them locations.
• Objective. Keep the highly connected blocks physically close to each other.
Placement:
• Goal. Assign the interconnect areas and the location of all the logic cells within
the flexible blocks.
• Objectives. Minimize the ASIC area and the interconnect density.
Global routing:
• Goal. Determine the location of all the interconnect.
• Objective. Minimize the total interconnect area used.
Detailed routing:
• Goal. Completely route all the interconnect on the chip.
• Objective. Minimize the total interconnect length used.
•64

Methods and Algorithms
• Each of the ASIC physical design steps, in general, belongs to a class
of mathematical problems known as NP-complete problems.
• Definition : This means that it is unlikely we can find an algorithm to solve
the problem exactly in polynomial time.
• Polynomial: If the time it takes to solve a problem increases with the size of
the problem at a rate that is polynomial but faster than quadratic (or worse
in an exponential fashion).
• A CAD tool needs methods or algorithms to generate a solution to each
problem using a reasonable amount of computer time.
•65

Measurement or objective function
Measurement or objective function:
We need to make a quantitative measurement of the quality of the solution
that we are able to find.
Often we combine several parameters or metrics that measure our
goals and objectives into a measurement function or Objective
function.
Cost Function :
If we are minimizing the measurement function, it is a cost function.
Gain function :
If we are maximizing the measurement function, we call the function a gain
function (sometimes just gain).
•66

ASIC Physical steps
• Each step of ASIC physical design steps are solved by:
– A set of goals and objectives
– A way to measure the goals and objectives
– Algorithm or method to find a solution that meets the goals and
objectives.
•67

VLSI Physical Design :- Partitioning
• System partitioning requires
– Goals and Objectives
– Methods and algorithms to find solutions
– Ways to evaluate these solutions.
• Goal of partitioning
– Divide the system into number of small systems.
• Objectives of Partitioning
we may need to take into account any or all of the following objectives:
– A maximum size for each ASIC
– A maximum number of ASICs
– A maximum number of connections for each ASIC
– A maximum number of total connections between all ASICs
•68

Measuring Connectivity
• Figure (a) shows a circuit schematic, netlist, or network.
• The network consists of circuit modules A–F. Equivalent terms for a
circuit module - cell, logic cell, macro, or a block.
• A cell or logic cell -a small logic gate (NAND etc.),collection of other
cells;
• Macro - gate-array cells;
• Block - a collection of gates or cells.
• Each logic cell has Electrical connections between the terminals-
connectors or pins.
• The network can be represented as the mathematical graph shown in
Figure (b).
• A graph is like a spider’s web:
– it contains vertexes (or vertices) A–F -graph nodes or points) that are
connected by edges.
– A graph vertex corresponds to a logic cell.
– An electrical connection (a net or a signal) between two logic cells
corresponds to a graph edge.
•70

Measuring Connectivity
• Net Cutset
– Divide the network into two by drawing a line across connections, make
net cuts. The resulting set of net cuts is the net cutset.
– Number of net cuts - the number of external connections between the
two partitions in a network.
• Edge cutset.
– When we divide the network graph into the same partitions we make
edge cuts and we create the edge cutset.
– Number of edge cuts – the number of external connections between the
two partitions in a graph
– Number of edge cuts in a graph is not necessarily equal to the
number of net cuts in the network. •72

Estimating ASIC size
• Estimate the die size of a 40 k-gate ASIC in a 0.35 µm gate array,
three-level metal process with 166 I/O pads.
• Die size includes core size and I/O size.
• Core size(logic and routing)=(gates/gate density) ×routing factor
×(1/gate array utilization)
– Gate density=standard cell density ×gate array utilization
• I/O size = a2 where a is the one side of die.
– One side of die= No of I/O pads in a side × I/O pad pitch
1µm(micron)=0.0393701mil
(1mil= Thousands of inch)
•73

• For this ASIC the minimum feature size is 0.35 µm.
• Gate Density:
• Gate density=standard cell density ×gate array utilization
• Core Size
• Core size(logic and routing)=(gates/gate density) ×routing factor
×(1/gate array utilization)
• [
•75

• Die size
• [No of I/O pads=166.
• No of pads per side
• =166/4=42 I/O pads per side.
• If a I/O pad pitch=5 mil then
• One side of die
=5×42=210mil
• Minimum requirement of die size to fit 166 I/O pads
=210×210=4.4×104mil2
• Die area utilized by core logic
=1.19×104/4.4×104mil2=27% . •76

A Simple Partitioning Example
•Goal : to partition our simple network into ASICs.
•Objectives are the following:
• -Use no more than three ASICs.
• -Each ASIC is to contain no more than four logic cells.
• -Use the minimum number of external connections for
each ASIC.
•FIGURE 15.7 Partitioning example.
• (a) We wish to partition this network into three ASICs with no more than four logic cells per ASIC.
• (b) A partitioning with five external connections (nets 2, 4, 5, 6, and 8)—the minimum number.
•78

• Splitting a network into several pieces - network partitioning
problem.
• Two types of algorithms used in system partitioning are
– Constructive partitioning - uses a set of rules to find a
solution.
– Iterative partitioning improvement (or iterative partitioning
refinement - takes an existing solution and tries to
improve it.
•Types of Partitioning
•80

Constructive Partitioning
• The most common constructive partitioning algorithms - seed growth or cluster
growth.
• The steps of a simple seed-growth algorithm for constructive partitioning:
1. Start a new partition with a seed logic cell.
2. Consider all the logic cells that are not yet in a partition. Select each of
these logic cells in turn.
3. Calculate a gain function, g(m) , that measures the benefit of adding
logic cell m to the current partition. One measure of gain is the number
of connections between logic cell m and the current partition.
4. Add the logic cell with the highest gain g(m) to the current partition.
5. Repeat the process from step 2. If you reach the limit of logic cells in a
partition, start again at step 1.
•81

• Seed Logic cell:
The logic cell with the most nets is a good choice as the
seed logic cell.
• Cluster:
A set of seed logic cells known as a cluster.
Called as clique —borrowed from graph theory.
• Clique:
A clique of a graph is a subset of nodes where each pair of
nodes is connected by an edge
•82

•A constructed partition using logic cell C as a seed. It is
difficult to get from this local minimum, with seven external
connections (2, 3, 5, 7, 9,11,12), to the optimum solution of b.
•83

Improvement in Partitioning
Fig 1 with 5 external connections Fig 2 with 7 external connections
•To get from the solution shown in Fig 2 to the solution of Fig 1,
which has a minimum number of external connections, requires a
complicated swap.
•The three pairs: D and F, J and K, C and L need to be swapped—
•84

Iterative Partitioning Improvement
Algorithm based on Interchange method and group migration method
Interchange method (swapping a single logic cell):
If the swap improves the partition, accept the trail interchange otherwise select a
new set of logic cells to swap.
Example: Greedy Algorithm –
It considers only one change
-Rejects it immediately if it is not an improvement.
-Accept the move only if it provides immediate benefit.
It is known as local minimum.
Group Migration (swapping a group of logic cell):
• Group migration consists of swapping groups of logic cells between partitions.
• The group migration algorithms –
– Adv: better than simple interchange methods at improving a solution
– Disadv: but are more complex.
Example: Kernighan – Lin Algorithm (K-L)
- Min cut Problem : Dividing a graph into two pieces, minimizing the
nets(edges) that are cut
•85

The Kernighan–Lin Algorithm
•86

The Kernighan–Lin Algorithm (contd.,)
• Total external cost, cut cost, cut weight
• External edge cost
• Internal edge cost
• Gain
where



B
b
A
a
ab
c
W
,



B
y
ay
a c
E



A
z
az
a c
I
ab
b
a C
D
D
g 2



a
a
a I
E
D 

•87

• The K–L algorithm finds a group of node pairs to swap that increases the gain
even though swapping individual node pairs from that group might decrease the
gain.
• The steps of K-L algorithm are:
1. Find two nodes, ai from A, and bi from B, so that the gain from swapping them is a
maximum. The gain gi is
2. Next pretend swap ai and bi even if the gain gi is zero or negative, and do not
consider ai and bi eligible for being swapped again.
3. Repeat steps 1 and 2 a total of m times until all the nodes of A and B have been
pretend swapped. We are back where we started, but we have ordered pairs of
nodes in A and B according to the gain from interchanging those pairs.
i
i
i
i b
a
b
a
i C
D
D
g 2



•88

4. Now we can choose which nodes we shall actually swap. Suppose we only swap the
first n pairs of nodes that we found in the preceding process. In other words we
swap nodes X = a1, a2, &…., an from A with nodes Y = b1, b2,&…..,bn from B.
The total gain would be,
5. We now choose n corresponding to the maximum value of Gn
• If the maximum value of Gn > 0, then swap the sets of nodes X and Y and thus
reduce the cut weight by Gn .
• Use this new partitioning to start the process again at the first step.
• If the maximum value of Gn = 0, then we cannot improve the current partitioning
and we stop.
• We have found a locally optimum solution.



n
i
i
n g
G
1
•89

•FIGURE 15.9 Partitioning a
graph using the Kernighan–Lin
algorithm.
•(a) Shows how swapping node 1
of partition A with node 6 of
partition B results in a gain of g =
2.
•(b) A graph of the gain resulting
from swapping pairs of nodes.
•(c) The total gain is equal to the
sum of the gains obtained at each
step.
•90

Kernighan-Lin Algorithm (1)
•Given:
Initial weighted graph G with
V(G) = { a, b, c, d, e, f }
•a
•c
•b
•d
•e •f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•Start with any partition of
V(G) into X and Y, say
•X = { a, c, e }
Y = { b, d, f }

KL algorithm (2a)
•cut-size = 3+1+2+4+6 = 16
• Da = Ea – Ia = – 3 (= 3 – 4 – 2)
• Dc = Ec – Ic = 0 (= 1 + 2 + 4 – 4 – 3)
• De = Ee – Ie = + 1 (= 6 – 2 – 3)
• Db = Eb – Ib = + 2 (= 3 + 1 –2)
• Dd = Ed – Id = – 1 (= 2 – 2 – 1)
• D = E – I = + 9 (= 4 + 6 – 1)
•Compute the gain values of moving
node x to the others set:
•Dx = Ex - Ix
Ex = cost of edges connecting node x
with the other group (extra)
Ix = cost of edges connecting node x
within its own group (intra)
•a
•c
•b
•d
•e •f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•X = { a, c, e }
Y = { b, d, f }

KL algorithm (2b)
• Da = Ea – Ia = – 3 (= 3 – 4 – 2)
• Db = Eb – Ib = + 2 (= 3 + 1 – 2)
• gab = Da + Db – 2cab = – 7 (= – 3 + 2 – 2.3)
•Cost saving when exchanging a and b is
essentially Da + Db
•However, the cost saving 3 of the direct
edge was counted twice. But this edge
still connects the two groups
•Hence, the real ―gain‖ (i.e. cost saving)
of this exchange is gab = Da + Db - 2cab
•a
•c
•b
•d
•e •f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•X = { a, c, e }
Y = { b, d, f }

KL algorithm (3)
• Da = –3 Db = +2
• Dc = 0 Dd = –1
• De = +1 Df = +9
• gab = Da + Db – 2cab = –3 + 2 – 23 = –7
• gad = Da + Dd – 2cad = –3 – 1 – 20 = –4
• gaf = Da + Df – 2caf = –3 + 9 – 20 = +6
• gcb = Dc + Db – 2ccb = 0 + 2 – 21 = 0
• gcd = Dc + Dd – 2ccd = 0 – 1 – 22 = –5
• gcf = Dc + Df – 2ccf = 0 + 9 – 24 = +1
• geb = De + Db – 2ceb = +1 + 2 – 20 = +3
• ged = De + Dd – 2ced = +1 – 1 – 20 = 0
• gef = De + Df – 2cef = +1 + 9 – 26 = –2
•Compute all the gains
•a
•c
•b
•d
•e •f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•cut-size = 16
•Pair with
maximum gain

KL algorithm (4)
•a
•c
•b
•d
•e
•f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•cut-size = 16 – 6 = 10
•a
•c
•b
•d
•e •f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•cut-size = 16
•Exchange nodes
a and f
•gaf = Da + Df – 2caf = –3 + 9 – 20 = +6
•Then lock up
nodes a and f

KL algorithm (5)
•a
•c
•b
•d
•e
•f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•cut-size = 10
•Update the G-values of unlocked nodes
• Da = –3 Db = +2
• Dc = 0 Dd = –1
• De = +1 Df = +9
• D’c = Dc + 2cca – 2ccf = 0 + 2(4 – 4) = 0
• D’e = De + 2cea – 2cef = 1 + 2(2 – 6) = –7
• D’b = Db + 2cbf – 2cba= 2 + 2(0 – 3) = –4
• D’d = Dd + 2cdf – 2cda = –1 + 2(1 – 0) = 1
•X’ = { c, e }
Y’ = { b, d }

KL algorithm (6)
•a
•c
•b
•d
•e
•f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•cut-size = 10
• D’c = 0 D’b = –4
• D’e = –7 D’d = +1
•X’ = { c, e }
Y’ = { b, d }
•Compute the gains
• g’cb = D’c + D’b – 2ccb = 0 – 4 – 21 = –6
• g’cd = D’c + D’d – 2ccd = 0 + 1 – 22 = –3
• g’eb = D’e + D’b – 2ceb = –7 – 4 – 20 = –
11
• g’ed = D’e + D’d – 2ced = –7 + 1 – 20 = –6
•Pair with maximum gain
(can also be neative)

KL algorithm (7)
•a
•c
•b
•d
•e
•f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•cut-size = 10
•Exchange nodes
c and d
•Then lock up
nodes c and d
•a
•d
•b
•c
•e
•f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•cut-size = 10 – (–3) = 13
•g’cd = D’c + D’d – 2ccd = 0 + 1 – 22 = –3

KL algorithm (8)
•cut-size = 13
•a
•d
•b
•c
•e
•f
•3
•1
•2
•4
•3 •4
•6
•2
•1
•2
•g”eb = D”e + D”b – 2ceb = –1 – 2 – 20 = –3
• D’c = 0 D’b = –4
• D’e = –7 D’d = +1
•X” = { e }
Y” = { b }
•Update the D-values of unlocked nodes
• D”e = D’e + 2ced – 2cec = –7 + 2(0 – 3) = –
1
• D”b = D’b + 2cbd – 2cbc= –4 + 2(2 – 1) = –
2
•Compute the gains
•Pair with max. gain
is (e, b)
• D’’b = –2 D’’e = –1

KL algorithm (9)
• Summary of the Gains…
– g = +6
– g + g’ = +6 – 3 = +3
– g + g’ + g” = +6 – 3 – 3 = 0
• Maximum Gain = g = +6
• Exchange only nodes a and f.
• End of 1 pass.
 Repeat the Kernighan-Lin.

Demerits of Kernighan–Lin Algorithm
• Minimizes the number of edges cut, not the number of nets cut.
• Does not directly allow for more than two partitions.
• Does not allow logic cells to be different sizes.
• Does not allow partitions to be unequal or find the optimum partition size.
• Does not allow for selected logic cells to be fixed in place.
• K-L Finding local optimum solution in random fashion
– Random starting partition
– Choice of nodes to swap may have equal gain
• Expensive in computation time.
– An amount of computation time that grows as for 2n nodes.
Solution:
To implement a net-cut partitioning rather than an edge-cut partitioning,
keep track of the nets rather than the edges – FM algorithm
n
n log
2
•101

•FIGURE - A hypergraph. (a) The network contains a net y with three terminals. (b) In the
network hypergraph we can model net y by a single hyperedge (B, C, D) and a star node. Now
there is a direct correspondence between wires or nets in the network and hyperedges in the graph
•Hypergraph- To represent nets with multiple terminals in a
network accurately
•A hypergraph consist of –
 a star- a special type of vertex
 a hyperedge- represents a net with more than two
terminals in a network.
Hypergraph
•102

Fiduccia-Mattheyses (F-M) Algorithm
• Addresses the difference between nets and edges.
• Reduce the computational time.
Key Features of F-M:
• Base logic cell - Only one logic cell moves at a time.
– Base logic cell is chosen to maintain balance between partitions in order to stop the
algorithm from moving all the logic cells to one large partition
– Balance - the ratio of total logic cell size in one partition to the total logic cell size in the
other. Altering the balance allows us to vary the sizes of the partitions.
• Critical nets - used to simplify the gain calculations.
– A net is a critical net if it has an attached logic cell that, when swapped, changes the
number of nets cut.
– It is only necessary to recalculate the gains of logic cells on critical nets that are attached
to the base logic cell.
• The logic cells that are free to move are stored in a doubly linked list. The lists are
sorted according to gain. This allows the logic cells with maximum gain to be found
quickly.
• Reduce the computation time - increases only slightly more than linearly with the
•103

Features of FM Algorithm
• Modification of KL Algorithm:
– Can handle non-uniform vertex weights (areas)
– Allow unbalanced partitions
– Extended to handle hypergraphs
– Clever way to select vertices to move, run much faster.

Ideas of FM Algorithm
• Similar to KL:
– Work in passes.
– Lock vertices after moved.
– Actually, only move those vertices up to the maximum
partial sum of gain.
• Difference from KL:
– Not exchanging pairs of vertices.
Move only one vertex at each time.
– The use of gain bucket data structure.

Gain Bucket Data Structure
•Cell
•#
•Cell
•#
•Max
•Gain
•+pmax
•-pmax
•1 •2 •n

FM Partitioning:
- each object is assigned a gain
- objects are put into a sorted
gain list
- the object with the highest
gain from the larger of the two
sides is selected and moved.
- the moved object is "locked"
- gains of "touched" objects are
recomputed
- gain lists are resorted
Object Gain: The amount of change in cut crossings that will occur if an object is
moved from its current partition into the other partition
Moves are made based on object gain

FM Partitioning:
-1
-2
-1
1
0
0
0
2
0
0
1
-
-1
-2

FM Partitioning:
-1
-2
-1
1
0
0
0
2
0
0
1
-
-1
-2
- Each object is assigned a
gain
- Objects are put into a sorted
gain list
- The object with the highest gain
from the larger of the two sides is
selected and moved.
- the moved object is "locked"
- gains of "touched" objects are
recomputed
- gain lists are resorted
Object Gain: The amount of change in cut crossings
that will occur if an object is moved from
its current partition into the other partition
Moves are made based on object gain.

-1
-2
-1
1
0
0
0
2
0
0
1
-
-1
-2
FM Partitioning:

-1
-2
-1
1
0
-2
-2
0
0
1
-
-1
-2
-2

-1
-2
1 -1
0
-2
-2
0
-2
-1
-
-1
-2
-2

-1
-2
1 -1
0
-2
-2 0
-2
-1
-
-1
-2
-2

-1
-2
1 -1
-2
-2
-2
0
-2
-1
1
-1
-2
-2

-1
-2
1
-1
-2
-2
-2
0
-2
-1
1
-1
-2
-2

-1
-2
-1
-3
-2
-2
-2
0
-2
-1
1
-1
-2
-2

-1
-2
-1
-3
-2
-2
-2
-2
-2
-1
-1
-1
-2
-2

Time Complexity of FM
• For each pass,
– Constant time to find the best vertex to move.
– After each move, time to update gain buckets is
proportional to degree of vertex moved.
– Total time is O(p), where p is total number of pins
• Number of passes is usually small.

Overcome problems in K-L using F-M
algorithm
• To generate unequal partitioning
– Dummy logic cells with no connections introduced in K-L algorithm
– Adjust partition size according to balance parameter in F-M
algorithm
• To fix logic cells in place during partitioning
– That logic cells should not be considered as base logic cells in F-M
algorithm.
•125

Ratio-Cut Algorithm
• Removes the restriction of constant partition sizes.
• The cut weight W for a cut that divides a network into two partitions, A
and B , is given by ,
• The ratio of a cut is defined as
R = W / ( |A| |B| )
The |A| and |B| are size of a partition is equal to the number of nodes it
contains (also known as the set cardinality). The cut that minimizes R is
called the ratio cut.



B
b
A
a
ab
c
W
,
•126

Ratio-Cut Algorithm (contd.,)
 A network is partitioned into small, highly connected groups
using ratio cuts.
 A reduced network is formed from these groups.
—Each small group of logic cells forms a node in the reduced network.
 Finally, apply the F–M algorithm to improve the reduced
network
Difference of Ratio-cut than K-L
The K–L algorithm minimizes W while keeping partitions
A and B the same size. •127

Look-ahead Algorithm
Why Look-ahead?
• K–L and F–M algorithms consider only the immediate gain to be made
by moving a node.
• When there is a tie between nodes with equal gain (as often happens), there is no
mechanism to make the best choice.
Algorithm
• The gain for the initial move is called as the first-level gain.
• Gains from subsequent moves are then second-level and higher gains.
• Define a gain vector that contains these gains.
• The choice of nodes to be swapped are found Using the gain vector .
• This reduces both the mean and variation in the number of cuts in the
resulting partitions.
•128

Look-ahead Algorithm
• Gain vector: Move 2 to B=+1, Move 3 to B=+1
• Gain vector: Move 5 to B=+1, Move 4 to B=+2
•129

Look-ahead Algorithm (contd.,)
•An example of network partitioning that shows the need to look ahead when
selecting logic cells to be moved between partitions.
•Partitionings (a), (b), and (c) show one sequence of moves – Partition I
•Partitionings (d), (e), and (f) show a second sequence – Partition II
•Partition I:
•The partitioning in (a) can be improved by moving node 2 from A to B with a
gain of 1. The result of this move is shown in (b). This partitioning can be
improved by moving node 3 to B, again with a gain of 1.
•Partition II:
•The partitioning shown in (d) is the same as (a). We can move node 5 to B
with a gain of 1 as shown in (e), but now we can move node 4 to B with a gain
•131

Simulated Annealing
• Takes an existing solution and then makes successive changes in a series
of random moves.
• Each move is accepted or rejected based on an energy function.
• In the Interchange method,
• Accept the new trial configuration only if the energy function decreases,
which means the new configuration is an improvement
• But in the simulated Annealing,
• Accept the new configuration even if the energy function increases for
the new configuration—which means things are getting worse.
• The probability of accepting a worse configuration is controlled by the
exponential expression exp(–∆E / T ),
where, ∆ E - the resulting increase in the energy function.
T - a variable that can be controlled and corresponds to the
temperature in the annealing of a metal cooling (this is why the process is called
simulated annealing).
•132

Simulated Annealing
• A parameter that relates the temperatures, T i and T i +1, at the i th and i + 1 th
iteration:
T i +1 =α T i .
• As the temperature is slowly decreased, the probability of making moves that
increase the energy function gets decreased.
• Cooling schedule – The critical parameter of the simulated-annealing algorithm is
the rate at which the temperature T is reduced.
• Finally, as the temperature approaches zero, refuse to make any moves that
increase the energy of the system and the system falls and comes to rest at the
nearest local minimum.
• The minimums of the energy function correspond to possible solutions.
• The best solution is the global minimum.
•133

Simulated Annealing
• Requirement of Simulated Annealing:
• To find a good solution, a local minimum close to the global minimum, requires a
high initial temperature and a slow cooling schedule.
• Disadvantage:
• This results in many trial moves and very long computer run time.(it gives
optimum)
• Advantage:
• To solve large graph problems
• Hill climbing- Accept moves that seemingly take us away from a desirable
solution to allow the system to escape from a local minimum and find other,
better, solutions.
•134

Other Partitioning Objectives
Constraints or
Objectivies
Purpose Implemented
Timing Constraints certain logic cells in a system
may need to be located on
the same ASIC in order to avoid
adding the delay of any external
interconnections
Adding weights to nets to make
them more important than others.
Power Constraints Some logic cells may consume
more power than others
To assign more than rough estimates
of power consumption for each logic
cell at the system planning stage,
before any simulation has been
completed.
Technology Constraints To include memory on an ASIC It will keep logic cell together
requiring similar technology
Cost Constraints To use low cost package To keep ASICs below a certain size.
Test Constraints Maintain Observability and
Controllability
It require that we force certain
connection to external
•135

FPGA Partitioning
- An asynchronous transfer mode (ATM)
connection simulator
• ATM is a signaling protocol for many different types of traffic including
constant bit rates (voice signals) as well as variable bit rates (compressed
video).
• The ATM Connection Simulator is a card that is connected to a
computer.
• Under computer control the card monitors and corrupts the ATM signals to
simulate the effects of real networks.
• An example would be to test different video compression algorithms.
Compressed video is very bursty (brief periods of very high activity),
has very strict delay constraints, and is susceptible to errors.
•136

•FIGURE 15.4 The asynchronous transfer mode (ATM) cell format. The ATM protocol uses
53-byte cells or packets of information with a data payload and header information for
routing and error control.
•Asynchronous transfer mode (ATM) cell format
•137

•An asynchronous transfer mode (ATM) connection
simulator
•138

FPGA Partitioning
• The simulator is partitioned into the three major blocks
• ATM traffic policer - which regulates the input to the simulator
• ATM cell delays generator – which delays ATM cell, reorders
ATM cells and inserts ATM cells with valid ATM cell headers.
• ATM cell error generator – which produce bit errors and four
random variables that are needed by the other two blocks.
• The Traffic Policer performs the following operations:
• Performs header screening and remapping.
• Checks ATM cell Conformance.
• Delete selected ATM Cells.
• The delay generator delays, misinserts and reorders the target ATM cells.
• The error generator performs the following operations:
• Payload bit error ratio generation: The user specifies the Bernoulli
probability PBER of the payload bit error ratio.
• Random variable generation for ATM cell loss, misinsertion,
reordering and deletion.
•139

Automatic Partitioning with FPGAs
• Altera hardware design language (AHDL)
- To direct the partitioner to automatically partition logic into chips
within the same family, using AUTO keyword,
DEVICE top_level IS AUTO ; % the partitioner assign logic
- CLIQUE keyword to keep logic together
CLIQUE fast_logic
BEGIN
| shift_register : MACRO;% keep this in one device
END;
•140

Power Dissipation
• Dynamic Power Dissipation
– Switching current from charging and discharging parasitic
capacitance.
– Short-circuit current when both n -channel and p -channel
transistors are momentarily on at the same time.
• Static Power Dissipation
– Subthresold current
– Leakage current
•141

Switching current
• From charging and discharging of parasitic capacitance
• When the p -channel transistor in an inverter is charging a capacitance, C ,
at a frequency, f ,
– the current through the transistor is I=C (d V /d t ).
– The power dissipation is P=VI=CV (d V /d t ) for one-half the period of the input, t =
1/(2 f ).
– The power dissipated in the p -channel transistor is thus
• When the n -channel transistor discharges the capacitor, the power
dissipation is equal.( ie., )
• Then total power dissipation,
• Most of the power dissipation in a CMOS ASIC arises from this source—the
switching current.
• The best way to reduce power is to reduce V DD and to reduce C , the amount
of capacitance we have to switch.

 

DD
V
DD
f
CV
CVdV
Pdt
0
2
2
1
0
2
1
2
1 DD
fCV
P 
2
2
1
DD
CV
•142

Short circuit current
• Both n-channel and p-channel transistors momentarily on at the same
time
• The short-circuit current or crowbar current can be particularly important
for output drivers and large clock buffers.
• For a CMOS inverter, the power dissipation due to the crowbar current is
, Transistor gain factor
– Where is the same for both p - and n -channel transistors.
– The threshold voltages Vtn are assumed equal for both transistor types.
– trf is the rise and fall time (assumed equal) of the input signal [ Veendrick,
1984].
 3
2 2
12
tn
DD
rf
V
V
ft
P 


  OX
C
L
W 
 
  DS
DS
tn
GS
DS
V
V
V
V
I









2
1

•143

Problem on Power Dissipation
• consider an output buffer that is capable of sinking 12mA at an output voltage
of 0.5 V., Derive the transistor gain factor (Assume VGS=VDD=3.3V; Vth =0.65V)
• If the output buffer is switching at 100 MHz and the input rise time to the
buffer is 2ns, Calculate the power dissipation due to short-circuit current.
• If the output load is 10 pF, Calculate the dissipation due to switching current.
• What do you infer from this?
• Inference:
(β=0.01AV-1, short-circuit current, P2=0.00133W or 1mW, switching
current, P1=0.01089W or 10mW)
– short-circuit current is typically less than 10 percent of the switching current.
•144

Subthreshold current
• CMOS transistor is never completely off
• When the gate-to-source voltage, VGS , of an MOS transistor is less than the
threshold voltage, Vt , the transistor conducts a very small subthreshold current in the
subthreshold region
– where I0 is a constant, and the constant, n, is normally between 1 and 2.
• The slope, S, of the transistor current in the subthreshold region is
• Find the slope of transistor current S at a junction temperature, T = 125 °C (400 K)
and assuming n = 1.5 ( assume q = 1.6 * 10 –19 Fm –1 , k = 1.38 * 10 –23 JK –1). What do
you infer from the result of slope of transistor current.
• Inference:
S = 120 mV/decade which does not scale.
The constant value of S = 120 mV/decade means it takes 120 mV to reduce the
subthreshold current by a factor of 10 in any process.







 1
exp
0
nKT
qV
I
I GS
DS
10
ln
q
nkT
S 
•145

Leakage Current
• Transistor leakage is caused by the fact that a reverse-biased diode conducts
a very small leakage current.
• The sources and drains of every transistor, as well as the junctions
between the wells and substrate, form parasitic diodes.
• The parasitic-diode leakage currents are strongly dependent on the
– type and quality of the process
– temperature.
• The parasitic diodes have two components in parallel: an area diode and a
perimeter diode.
• The leakage current due to perimeter diode is larger than area diode.
• The ideal parasitic diode currents are given by the following equation:







 1
exp
nKT
qV
I
I D
s
•146

UNIT III
FLOORPLANNING
Dr.K.Kalyani
AP, ECE,
TCE.
•147

Introduction
• The input to the floorplanning step - output of system partitioning and
design entry—a netlist.
• Netlist - describing circuit blocks, the logic cells within the blocks, and
their connections.
•FIGURE 16.3 Interconnect and
gate delays. As feature sizes
decrease, both average
interconnect delay and average
gate delay decrease—but at
different rates. This is because
interconnect capacitance tends to a
limit that is independent of scaling.
Interconnect delay now
dominates gate delay.
•Floor planning - To predict interconnect delay by
estimating interconnect length.
•148

•The starting point of floorplaning and placement steps for
the viterbi decoder
•-collection of standard cells with no room set aside yet for
routing. •149

The starting point of floorplaning and
placement steps for the viterbi decoder
• Small boxes that look like bricks - outlines of the standard cells.
• Largest standard cells, at the bottom of the display (labeled dfctnb)
- 188 D flipflops.
• '+' symbols -drawing origins of the standard cells—for the D flip-flops
they are shifted to the left and below the logic cell bottom left-hand
corner.
• Large box surrounding all the logic cells - estimated chip size.
• (This is a screen shot from Cadence Cell Ensemble.)
•150

The viterbi decoder after floorplanning and placement
•151

The viterbi decoder after floorplanning
and placement
• 8 rows of standard cells separated by 17 horizontal
channels (labeled 2–18).
• Channels are routed as numbered.
• In this example, the I/O pads are omitted to show the cell
placement more clearly.
•152

Floorplanning Goals and Objectives
• The input to a floorplanning tool is a hierarchical netlist that describes
– the interconnection of the blocks (RAM, ROM, ALU, cache controller, and so on)
– the logic cells (NAND, NOR, D flip-flop, and so on) within the blocks
– the logic cell connectors (terminals , pins , or ports)
• The netlist is a logical description of the ASIC;
• The floorplan is a physical description of an ASIC.
• Floorplanning is a mapping between the logical description (the
netlist) and the physical description (the floorplan).
The Goals of Floorplanning are to:
• Arrange the blocks on a chip,
• Decide the location of the I/O pads,
• Decide the location and number of the power pads,
• Decide the type of power distribution, and
• Decide the location and type of clock distribution.
Objectives of Floorplanning –
To minimize the chip area
To minimize delay.
Measuring area is straightforward, but measuring delay is more difficult
•153

Measurement of Delay in Floor planning
•FIGURE 16.4 Predicted capacitance. (a) Interconnect lengths as a function of fanout (FO) and circuit-block
size. (b) Wire-load table. There is only one capacitance value for each fanout (typically the average value).
(c) The wire-load table predicts the capacitance and delay of a net (with a considerable error). Net A and net
B both have a fanout of 1, both have the same predicted net delay, but net B in fact has a much greater delay
than net A in the actual layout (of course we shall not know what the actual layout is until much later in the
design process). •154

(contd.,)
• A floorplanning tool can use predicted-capacitance tables (also
known as interconnect-load tables or wire-load tables ).
• Typically between 60 and 70 percent of nets have a FO = 1.
• The distribution for a FO = 1 has a very long tail, stretching to
interconnects that run from corner to corner of the chip.
• The distribution for a FO = 1 often has two peaks, corresponding to
a distribution for close neighbors in subgroups within a block,
superimposed on a distribution corresponding to routing between
subgroups.
•155

(contd.,)
• We often see a twin-peaked distribution at the chip level also, corresponding
to separate distributions for interblock routing (inside blocks) and
intrablock routing (between blocks).
• The distributions for FO > 1 are more symmetrical and flatter than for FO =
1.
• The wire-load tables can only contain one number, for example the
average net capacitance, for any one distribution.
• Many tools take a worst-case approach and use the 80- or 90-percentile point
instead of the average. Thus a tool may use a predicted capacitance for
which we know 90 percent of the nets will have less than the estimated
capacitance.
•156

• Repeat the statistical analysis for blocks with different sizes.
For example, a net with a FO = 1 in a 25 k-gate block will have a different
(larger) average length than if the net were in a 5 k-gate block.
• The statistics depend on the shape (aspect ratio) of the block
(usually the statistics are only calculated for square blocks).
• The statistics will also depend on the type of netlist.
For example, the distributions will be different for a netlist generated by
setting a constraint for minimum logic delay during synthesis—which tends
to generate large numbers of two-input NAND gates—than for netlists
generated using minimum-area constraints.
(contd.,)
•157

Floorplanning Tools
• Floorplanning in CBIC:
• Flexible blocks (or variable blocks ) :
– Their total area is fixed,
– Their shape (aspect ratio) and connector locations may be adjusted during the placement.
• Fixed blocks:
– The dimensions and connector locations of the other fixed blocks (perhaps RAM, ROM, compiled
cells, or megacells) can only be modified when they are created.
• Seeding:
– Force logic cells to be in selected flexible blocks by seeding . We choose seed cells by name.
– Seeding may be hard or soft.
• Hard seed - fixed and not allowed to move during the remaining floor
planning and placement steps.
• Soft seed - an initial suggestion only and can be altered if necessary by the
floor planner.
• Seed connectors within flexible blocks—forcing certain nets to appear in a
specified order, or location at the boundary of a flexible block.
• Rat’s nest:-display the connection between the blocks
• Connections are shown as bundles between the centers of blocks or as flight
lines between connectors.
•158

Floorplanning Tools
Floorplanning a cell-based ASIC.
(a) Initial floorplan generated by the floorplanning tool. Two of the blocks are flexible (A and C)
and contain rows of standard cells (unplaced). A pop-up window shows the status of block A.
(b) An estimated placement for flexible blocks A and C. The connector positions are known and a
rat’s nest display shows the heavy congestion below block B.
(c) Moving blocks to improve the floorplan.
(d) The updated display shows the reduced congestion after the changes.
•159

(a) The initial floorplan with a 2:1.5 die aspect ratio.
(b) Altering the floorplan to give a 1:1 chip aspect ratio.
Congestion analysis-One measure of congestion is the difference between the number of
interconnects that we actually need, called the channel density , and the channel capacity
(c) A trial floorplan with a congestion map. Blocks A and C have been placed so that we know the terminal
positions in the channels. Shading indicates the ratio of channel density to the channel capacity. Dark areas
show regions that cannot be routed because the channel congestion exceeds the estimated capacity.
(d) Resizing flexible blocks A and C alleviates congestion.
•Aspect ratio and Congestion
Analysis
•160

Channel Definition
•Channel definition or channel allocation
•During the floorplanning step, assign the areas between blocks that are to be
used for interconnect.
•Routing a T-junction between two channels in two-level metal.
•The dots represent logic cell pins.
•(a) Routing channel A (the stem of the T) first allows us to adjust the width of channel
B. (b) If we route channel B first (the top of the T), this fixes the width of channel A.
•Route the stem of a T-junction before route the top.
•161

Channel Routing
•Defining the channel routing order for a slicing floorplan using a slicing tree.
•(a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each
piece contains just one circuit block. Each cut divides a piece into two without cutting
through a circuit block.
•(b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks
are left.
•(c) The slicing tree corresponding to the sequence of cuts gives the order in which to route
the channels: 4, 3, 2, and finally 1.
•162

Cyclic Constraints
•Cyclic constraints.
•(a) A nonslicing floorplan with a cyclic constraint that prevents channel routing.
(b) In this case it is difficult to find a slicing floorplan without increasing the chip
area.
•(c) This floorplan may be sliced (with initial cuts 1 or 2) and has no cyclic
constraints, but it is inefficient in area use and will be very difficult to route.
•163

Cyclic Constraints
•
•(a) We can eliminate the cyclic constraint by merging the blocks A and C.
•(b) A slicing structure.
•164

I/O and Power Planning (contd.,)
• Every chip communicates with the outside world. Signals
flow onto and off the chip and we need to supply power.
• The I/O and power constraints has to considered early in
the floorplanning process.
• A silicon chip or die (plural die, dies, or dice) is mounted
on a chip carrier inside a chip package .
• Connections are made by bonding the chip pads to fingers
on a metal lead frame that is part of the package.
• The metal lead-frame fingers connect to the package pins
. A die consists of a logic core inside a pad ring .
•165

I/O and Power Planning
•FIGURE 16.12 Pad-limited and core-limited die.
•(a) A pad-limited die. Tall, thin pad-limited pads, which
maximize the number of pads we can fit around the outside
of the chip. The number of pads determines the die size.
•(b) A core-limited die: short, wide core-limited pads.The
core logic determines the die size.
• (c) Using both pad-limited pads and core-limited pads
•166

• Power Pads and I/O Pads:
• Special power pads are used for:1. positive supply, or VDD, power buses
(or power rails ) and
2. ground or negative supply, VSS or GND.
• One set of VDD/VSS pads supplies power to the I/O pads only.
• Another set of VDD/VSS pads connects to a second power ring that supplies the
logic core.
• The I/O power is a dirty power since it has to supply large transient currents to
the output transistors. We keep dirty power separate to avoid injecting noise
into the internal-logic power (the clean power ).
• I/O pads also contain special circuits to protect against electrostatic discharge
( ESD ). These circuits can withstand very short high-voltage (several kilovolt)
pulses that can be generated during human or machine handling.
•167

• Pad Seed: Fix the position of the chip pad for down
bonding
• Making an electrical connection between the substrate
and a chip pad, or to a package pin, it must be to VDD ( n
-type substrate) or VSS ( p -type substrate). This substrate
connection (for the whole chip) employs a down bond (or
drop bond) to the carrier. We have several options:
 Dedicate one (or more) chip pad(s) to down bond to
the chip carrier.
 Make a connection from a chip pad to the lead
frame and down bond from the chip pad to the chip
carrier.
 Make a connection from a chip pad to the lead
frame and down bond from the lead frame.
 Down bond from the lead frame without using a
chip pad.
 Leave the substrate and/or chip carrier
unconnected.
• Depending on the package design, the type and positioning
of down bonds may be fixed.
• This means we need to fix the position of the chip pad for
down bonding using a pad seed
•168

• A double bond connects two pads to one chip-carrier finger and one package
pin. We can do this to save package pins or reduce the series inductance of
bond wires (typically a few nanohenries) by parallel connection of the pads.
• Multiple VDD and VSS pads:
• To reduce the series resistive and inductive impedance of power supply
networks, it is normal to use multiple VDD and VSS pads.
• This is particularly important with the simultaneously switching outputs (
SSOs ) that occur when driving buses .
• The output pads can easily consume most of the power on a CMOS ASIC,
because the load on a pad (usually tens of picofarads) is much larger than
typical on-chip capacitive loads.
• Depending on the technology it may be necessary to provide dedicated VDD
and VSS pads for every few SSOs. Design rules set how many SSOs can be
used per VDD/VSS pad pair. These dedicated VDD/VSS pads must “follow”
groups of output pads as they are seeded or planned on the floorplan.
•169

• Using a pad mapping we translate the logical pad in a netlist to a physical pad from a
pad library . We might control pad seeding and mapping in the floorplanner.
• Handling of I/O pads can become quite complex; there are several nonobvious
factors that must be considered when generating a pad ring:
• Design library pad cells for one orientation.
– For example, an edge pad for the south side of the chip, and a corner pad
for the southeast corner.
• We could then generate other orientations by rotation and flipping (mirroring).
Some ASIC vendors will not allow rotation or mirroring of logic cells in the
mask file.
• To avoid these problems we may need to have separate horizontal, vertical,
left-handed, and right-handed pad cells in the library with appropriate logical
to physical pad mappings.
• If we mix pad-limited and core-limited edge pads in the same pad ring, this
complicates the design of corner pads. Usually the two types of edge pad cannot
abut. In this case a corner pad also becomes a pad-format changer , or
hybrid corner pad .
• In single-supply chips we have one VDD net and one VSS net, both global power
nets . It is also possible to use mixed power supplies (for example, 3.3 V and
5 V) or multiple power supplies ( digital VDD, analog VDD).
•170

•FIGURE 16.13 Bonding pads. (a) This chip uses both pad-limited and core-limited
pads. (b) A hybrid corner pad. (c) A chip with stagger-bonded pads. (d) An area-
bump bonded chip (or flip-chip). The chip is turned upside down and solder bumps
connect the pads to the lead frame
•171

• Other I/O bond:
• stagger-bond arrangement using two rows of I/O pads. In this case the design
rules for bond wires (the spacing and the angle at which the bond wires leave
the pads) become very important.
• Area-bump bonding arrangement (also known as flip-chip, solder-bump)
used, for example, with ball-grid array ( BGA ) packages.
• Even though the bonding pads are located in the center of the chip, the I/O
circuits are still often located at the edges of the chip because of difficulties in
power supply distribution and integrating I/O circuits together with logic in
the center of the die.
• I/O pads in MGA and CBIC:
• In an MGA the pad spacing and I/O-cell spacing is fixed—each pad occupies a
fixed pad slot (or pad site ). This means that the properties of the pad I/O are
also fixed but, if we need to, we can parallel adjacent output cells to increase
the drive. To increase flexibility further the I/O cells can use a separation, the
I/O-cell pitch , that is smaller than the pad pitch .
•172

•FIGURE 16.14 Gate-array I/O pads. (a) Cell-based
ASICs may contain pad cells of different sizes and
widths. (b) A corner of a gate-array base. (c) A
gate-array base with different I/O cell and pad
pitches
•173

• The long direction of a rectangular channel is the channel spine .
• Some automatic routers may require that metal lines parallel to a channel
spine use a preferred layer (either m1, m2, or m3). Alternatively we say that
a particular metal layer runs in a preferred direction .

•FIGURE 16.15 Power distribution. (a) Power distributed using m1 for VSS and m2 for VDD. This helps
minimize the number of vias and layer crossings needed but causes problems in the routing channels.
(b) In this floorplan m1 is run parallel to the longest side of all channels, the channel spine. This can
make automatic routing easier but may increase the number of vias and layer crossings. (c) An
expanded view of part of a channel (interconnect is shown as lines). If power runs on different layers
along the spine of a channel, this forces signals to change layers. (d) A closeup of VDD and VSS buses as
they cross. Changing layers requires a large number of via contacts to reduce resistance.

Power distribution.
• (a) Power distributed using m1 for VSS and m2 for VDD.
– This helps minimize the number of vias and layer crossings needed
– but causes problems in the routing channels.
• (b) In this floorplan m1 is run parallel to the longest side of all
channels, the channel spine.
– This can make automatic routing easier
– but may increase the number of vias and layer crossings.
• (c) An expanded view of part of a channel (interconnect is shown as
lines). If power runs on different layers along the spine of a channel,
this forces signals to change layers.
• (d) A closeup of VDD and VSS buses as they cross. Changing layers
requires a large number of via contacts to reduce resistance.

Clock Planning
• clock spine routing scheme with all clock pins driven directly from the clock
driver. MGAs and FPGAs often use this fish bone type of clock distribution
scheme
• clock skew and clock latency
•FIGURE 16.16 Clock distribution.
•(a) A clock spine for a gate array.
•(b) A clock spine for a cell-based ASIC
(typical chips have thousands of clock
nets).
•(c) A clock spine is usually driven from
one or more clock-driver cells. Delay in
the driver cell is a function of the
number of stages and the ratio of output
to input capacitance for each stage
(taper).
•(d) Clock latency and clock skew. We
would like to minimize both latency and
skew.

Clock Planning (cont.,)
• FIGURE 16.17 A clock tree. (a) Minimum delay is achieved when the taper of
successive stages is about 3. (b) Using a fanout of three at successive nodes.
(c) A clock tree for the cell-based ASIC of Figure 16.16 b. We have to balance
the clock arrival times at all of the leaf nodes to minimize clock skew.

Placement Methods
Dr.K.Kalyani
AP, ECE,
TCE
•179

Introduction
• After completion of floorplan, placement of the logic cells within the
flexible blocks takes place.
• Placement is much more suited to automation than floorplanning.
• After completion of floorplanning and placement, we can predict both
intrablock and interblock capacitances
•180

Placement Terms and Definitions
• CBIC, MGA, and FPGA architectures all have rows of logic cells separated by
the interconnect—these are row-based ASICs
• INTERCONNECT STRUCTURE. (a) The two-level metal CBIC floorplan
•(b) A channel from the flexible block A. This channel has a channel height equal to the
maximum channel density of 7
•(c) A channel that uses OTC (over-the-cell) routing in m2. •181

• GATE-ARRAY INTERCONNECT.
•(a) A small two-level metal gate array (about 4.6 k-gate).
•(b) Routing in a block.
•(c) Channel routing showing channel density and channel capacity. The channel height on a gate array
may only be increased in increments of a row. If the interconnect does not use up all of the channel, the
rest of the space is wasted. The interconnect in the channel runs in m1 in the horizontal direction with
m2 in the vertical direction.
•182

Some commonly used terms:
• Vertical interconnect uses feedthroughs to cross the logic cells.
• FEEDTHROUGH or JUMPER - A vertical strip of metal that runs from the top to
bottom of a cell (for double-entry cells ), but has no connections inside the cell.
• FEEDTHROUGH CELL (or crosser cell ) A dedicated empty cell (with no logic)
that can hold one or more vertical interconnects
• UNCOMMITTED FEEDTHROUGH (also BUILT-IN FEEDTHROUGH , IMPLICIT
FEEDTHROUGH , or JUMPER ) - An unused vertical track (or just track ) in a
logic cell.
• FEEDTHROUGH PIN or FEEDTHROUGH TERMINAL - is an input or output
that has connections at both the top and bottom of the standard cell.
• SPACER CELL (usually the same as a feedthrough cell) is used to fill space in
rows so that the ends of all rows in a flexible block may be aligned to connect to
power buses.
• ELECTRICALLY EQUIVALENT CONNECTORS (OR EQUIPOTENTIAL
CONNECTORS ) - Two connectors for the same physical net.
• LOGICALLY EQUIVALENT CONNECTORS (or FUNCTIONALLY EQUIVALENT
CONNECTORS, EQUIVALENT CONNECTORS) Example: The two inputs of a
two-input NAND gate may be logically equivalent connectors •183

Interconnect Area for CBIC,MGA and FPGA
HORIZONTAL INTERCONNECT
• Channeled gate arrays and FPGAs, the horizontal interconnect areas—the channels,
usually on m1—have a fixed capacity.
• The channel capacity of CBICs and channelless MGAs can be expanded to hold as
many interconnects as are needed.
VERTICAL INTERCONNECT
• In the vertical interconnect direction, usually m2, FPGAs still have fixed resources.
• In contrast the placement tool can always add vertical feedthroughs to a channeled
MGA, channelless MGA, or CBIC.
•184

Placement Goals and Objectives
Goal of a placement –
To arrange all the logic cells within the flexible blocks on a chip.
Ideally, the objectives of the placement step are to
• Guarantee the router can complete the routing step
• Minimize all the critical net delays
• Make the chip as dense as possible
Additional objectives:
• Minimize power dissipation
• Minimize cross talk between signals
The most commonly used placement objectives (by current Placement
tools):
• Minimize the total estimated interconnect length
• Minimize the interconnect congestion
• Meet the timing requirements for critical nets
•185

Measurement of Placement Goals and Objectives
- Interconnect length
• Trees on graphs - The graph structures that correspond to making all the
connections for a net.
• Steiner trees —Special classes of trees-minimize the total length of
interconnect.
• Steiner tree (Rectilinear routing or Manhattan routing) - This type of tree
uses diagonal connections—solving problem using interconnects on a
rectangular grid.
– Use Manhattan distance than Euclidean distance.
• Euclidean distance between two points is the straight-line distance.
• Manhattan distance - rectangular distance.
• Minimum rectilinear Steiner tree ( MRST ) - shortest interconnect using a
rectangular grid. The determination of the MRST is in general an NP-
complete problem—which means it is hard to solve.
•186

•Placement using trees on graphs. (a) The floorplan
•(b) An expanded view of the flexible block A showing four rows of standard cells for placement (typical
blocks may contain thousands or tens of thousands of logic cells). We want to find the length of the net
shown with four terminals, W through Z, given the placement of four logic cells (labeled: A.211, A.19,
A.43, A.25). (c) The problem for net (W, X, Y, Z) drawn as a graph. The shortest connection is the
minimum Steiner tree. (d) The minimum rectilinear Steiner tree using Manhattan routing. The
rectangular (Manhattan) interconnect-length measures are shown for each tree
•187

Measurement of Placement (contd.,)
Interconnect Length
• Complete graph has connections from each terminal to every other terminal.
• Complete-graph measure adds all the interconnect lengths of the complete-
graph connection together and then divides by n /2, where n is the number of
terminals.
Complete graph = (n ( n -1) ) / 2 )
• Bounding box - the smallest rectangle that encloses all the terminals.
• Half-perimeter measure (or bounding-box measure) –
one-half the perimeter of the bounding box.
Half perimeter f = ½ Σm
i=1 hi
where m is the nets, hi is the half perimeter measure for net i.
•188

Interconnect-length measures.
(a) Complete-graph measure. (b) Half-perimeter measure.
•189

Correlation between total length of chip interconnect and
the half-perimeter and complete-graph measures.
• Meander factor that specifies, on average, the ratio of the interconnect
created by the routing tool to the interconnect-length estimate used by the
placement tool.
• Another problem is MRST that minimizes total net length may not
minimize net delay.
•190

Interconnect Congestion
• There is no point in minimizing the interconnect length if we create a
placement that is too congested to route.
• If we use minimum interconnect congestion as an additional placement
objective, we need some way of measuring it.
• What we are trying to measure is interconnect density
• One measure of interconnect congestion uses the maximum cut line .
• Maximum cut line: Imagine a horizontal or vertical line drawn anywhere
across a chip or block, The number of interconnects that must cross this
line is the cut size (the number of interconnects we cut).
• The maximum cut line has the highest cut size.
•191

• Interconnect congestion for the cell-based ASIC.
•(a) Measurement of congestion.
•(b) An expanded view of flexible block A shows a
maximum cut line.
•192

Interconnect Delay
• Many placement tools minimize estimated interconnect length or
interconnect congestion as objectives.
• The problem with this approach is that a logic cell may be placed a
long way from another logic cell to which it has just one
connection. However, the one long connection may be critical as
far as timing delay is concerned.
• As technology is scaled, interconnection delays become larger
relative to circuit delays and this problem gets worse.
• The minimum-length Steiner tree does not necessarily
correspond to the interconnect path that minimizes delay.
•193

Interconnect Delay
• Half-perimeter measure
• In the placement phase typically a simple interconnect length
approximation is taken to this minimum-delay path .
• Timing-driven placement
• In timing-driven placement, estimate delay for every net for every trial
placement, possibly for hundreds of thousands of gates.
• Parameters to estimate Interconnect Delay
• No information on which layers and how many vias the interconnect will
use or how wide it will be. Some tools allow us to include estimates for these
parameters.
• Specification of metal usage, the percentage of routing on the different
layers to expect from the router, allows the placement tool to estimate RC
values and delays—and thus minimize delay.
•194

Placement Algorithms
There are two classes of placement algorithms used in CAD tools:
 Constructive placement - uses a set of rules to arrive at a constructed
placement.
Example :min-cut algorithm. Eigenvalue method.
 Iterative placement improvement.
As in system partitioning, placement usually starts with a constructed solution and then
improves it using an iterative algorithm.
Min-cut placement method
- uses successive application of partitioning. The steps are,
– Cut the placement area into two pieces.
– Swap the logic cells to minimize the cut cost.
– Repeat the process from step 1, cutting smaller pieces until all the logic
cells are placed
Usually we divide the placement area into bins .
The size of a bin can vary, from a bin size equal to the base cell (for a gate array) to a
bin size that would hold several logic cells.
We can start with a large bin size, to get a rough placement, and then reduce the
in size to get a final placement.
•195

•Min-cut placement. (a) Divide the chip into bins using a grid.
•(b) Merge all connections to the center of each bin.
•(c) Make a cut and swap logic cells between bins to minimize the cost of the cut.
•(d) Take the cut pieces and throw out all the edges that are not inside the piece.
•(e) Repeat the process with a new cut and continue until we reach the individual bins.
•196

Placement Algorithms (contd.,)
The eigenvalue placement algorithm uses the cost matrix or weighted connectivity matrix (eigen
value methods are also known as spectral methods ).
The measure we use is a cost function f that we shall minimize, given by ,
(1)
where C = [ cij ] is the (possibly weighted) connectivity matrix, and d ij is the Euclidean distance
between the centers of logic cell i and logic cell j .
Since we are going to minimize a cost function that is the square of the distance between logic cells,
these methods are also known as quadratic placement methods.
This type of cost function leads to a simple mathematical solution. We can rewrite the cost function f in
matrix form:
B is a symmetric matrix, the disconnection matrix (also called the Laplacian).
B= D- C



n
i
ij
ijd
c
f
1
2
2
1
   
By
y
Bx
x
f
y
y
x
x
c
f
T
T
n
j
i
j
i
j
i
ij





 
1
,
2
2
2
1
•197

where,
We can simplify the problem by noticing that it is symmetric in the x - and y -coordinates.
Let us solve the simpler problem of minimizing the cost function for the placement of logic
cells along just the x – axis first.
We can then apply this solution to the more general two-dimensional placement problem.
Before we solve this simpler problem, we introduce a constraint that the coordinates of the logic
cells must correspond to valid positions (the cells do not overlap and they are placed on-grid).
We make another simplifying assumption that all logic cells are the same size and we must place
them in fixed positions.
We can define a vector p consisting of the valid positions:
(4)
For a valid placement the x -coordinates of the logic cells,
(5)
must be a permutation of the fixed positions, p . We can show that requiring the logic cells to be in
fixed positions in this way leads to a series of n equations restricting the values of the logic cell
coordinates .If we impose all of these constraint equations the problem becomes very complex.
Instead we choose just one of the equations:
(6)

 


n
i
i
n
i
i p
x
1
2
1
2
j
i
d
C
d
ij
n
j
ij
ii


 

,
0
1
 
n
p
p
p
p ....
, 2
1

 
n
x
x
x
x ,...
, 2
1

•198

Simplifying the problem in this way will lead to an approximate solution
to the placement problem.
We can write this single constraint on the x -coordinates in matrix form:
where P is a constant.




n
i
i
T
p
P
P
x
x
1
2
•199

We can now summarize the formulation of the problem, with the simplifications that we have made, for a
one-dimensional solution. We must minimize a cost function, g, where
(8)
subject to the constraint:
(9)
This is a standard problem that we can solve using a Lagrangian multiplier:
(10)
To find the value of x that minimizes g we differentiate partially with respect to x and set the
result equal to zero. We get the following equation:
(11)
This last equation is called the characteristic equation for the disconnection matrix B and occurs
frequently in matrix algebra (this l has nothing to do with scaling).
The solutions to this equation are the eigenvectors and eigenvalues of B .
Multiplying Eq.(11) by x T we get:
However, since we imposed the constraint x T x = P and x T Bx = g , then
The eigenvectors of the disconnection matrix B are the solutions to our placement problem.
Bx
x
g T

 
p
x
x
Bx
x T
T



 
p
x
xT

  0

 x
I
B 
Bx
x
x
x T
T


p
g



•200

(11)
This last equation is called the characteristic equation for
the disconnection matrix B and occurs frequently in matrix
algebra (this l has nothing to do with scaling).
The solutions to this equation are the eigenvectors and
eigenvalues of B .
  0

 x
I
B 
•201

Eigenvalue placement problem
• λ4-6λ3+10λ2-4λ=0
• λ=0,0.585,3.414,2
•202
  0

 x
I
B 
• B= D- C

Iterative Placement Improvement
An iterative placement improvement algorithm takes an existing placement and
tries to improve it by moving the logic cells. There are two parts to the
algorithm:
– The selection criteria that decides which logic cells to try moving.
– The measurement criteria that decides whether to move the selected cells.
There are several interchange or iterative exchange methods that differ in their
selection and measurement criteria:
– Pair wise interchange,
– force-directed interchange,
– force-directed relaxation, and
– force-directed pair wise relaxation.
All of these methods usually consider only pairs of logic cells to be exchanged.
A source logic cell is picked for trial exchange with a destination logic cell.
•204

(contd.,)
The pair wise-interchange algorithm
– Select the source logic cell at random.
– Try all the other logic cells in turn as the destination logic cell.
– Use any of the measurement methods we have discussed to decide on
whether to accept the interchange.
– The process repeats from step 1, selecting each logic cell in turn as a
source logic cell.
Neighborhood exchange algorithm
• Modification to pairwise interchange that considers only destination
logic cells in a neighborhood —cells within a certain distance, e, of
the source logic cell.
• Limiting the search area for the destination logic cell to the e -
neighborhood reduces the search time.
•205

•Pair-wise Interchange.
• (a) Swapping the source logic cell with a destination logic cell in pairwise
interchange.
•(b) Sometimes we have to swap more than two logic cells at a time to reach an
optimum placement, but this is expensive in computation time. Limiting the search
to neighborhoods reduces the search time. Logic cells within a distance e of a logic
cell form an e-neighborhood.
•(c) A one-neighborhood.
•(d) A two-neighborhood.
•206

- Force-directed placement method
• Imagine connecting all the logic cells which are going to place are
connected through identical springs .
•The number of springs is equal to the number of connections between logic
cells.
•The effect of the springs is to pull connected logic cells together.
•The more highly connected the logic cells, the stronger the pull of the springs.
• The force on a logic cell i due to logic cell j is given by Hooke’s law , which
says the force of a spring is proportional to its extension:
Fij = – c ij xij .
– The vector component xij is directed from the center of logic cell i to the center of
logic cell j .
– The vector magnitude is calculated as either the Euclidean or Manhattan distance
between the logic cell centers.
– The cij form the connectivity or cost matrix (the matrix element cij is the number of
connections between logic cell i and logic cell j ).
•207

•FIGURE 16.27 Force-directed placement.
• (a) A network with nine logic cells.
• (b) We make a grid (one logic cell per bin).
• (c) Forces are calculated as if springs were attached to
the centers of each logic cell for each connection.The
two nets connecting logic cells A and I correspond to
two springs.
•(d) The forces are proportional to the spring
extensions.
•208

(contd.,)
Force-directed placement algorithms:
 The force-directed interchange algorithm uses the force vector to select a
pair of logic cells to swap.
 The force-directed relaxation a chain of logic cells is moved.
 The force-directed pairwise relaxation algorithm swaps one pair of logic
cells at a time.
` Force-directed solution minimize the energy of the system, corresponding
to minimizing the sum of the squares of the distances separating logic
cells.
Force-directed placement algorithms thus also use a quadratic cost function.
•209

•FIGURE 16.28 Force-directed iterative
placement improvement.
•(a) Force-directed interchange.
•(b) Force-directed relaxation.
•(c) Force-directed pairwise relaxation.
•210

Placement Using Simulated Annealing
Applying simulated annealing to placement, the algorithm is as follows:
– Select logic cells for a trial interchange, usually at random.
– Evaluate the objective function E for the new placement.
– If DE is negative or zero, then exchange the logic cells.
– If DE is positive, then exchange the logic cells with a probability of
exp(–DE/T).
– Go back to step 1 for a fixed number of times, and then lower the
temperature T according to a cooling schedule: Tn +1 = 0.9 Tn , for
example.
Comparison of Placement Algorithms
- Min-cut based constructive placement is faster than simulated annealing .
–Simulated annealing is capable of giving better results at the expense of
long computer run times.
–The iterative improvement methods that described earlier are capable of
giving results as good as simulated annealing, but they use more complex
algorithms. •211

Timing-Driven Placement Methods
Minimizing delay is becoming more and more important as a placement
objective.
There are two main approaches:
 net based
 path based.
We know that we can use net weights in our algorithms.
• The net weights might then be the number of times each net appears in
this list.
• The problem is to calculate the weights.
One method finds the n most critical paths.
•212

• Find the net weights uses the zero-slack algorithm [ Hauge et al.,1987].
Figure 16.29 shows how this works (all times are in nanoseconds).
• Primary inputs at which the arrival times (this is the original definition,
some people use the term actual times ) of each signal are known.
• Required times for the primary outputs —the points in time at which the
signals to be valid.
• Work forward from the primary inputs and backward from the primary
outputs to determine arrival and required times at each input pin for each net.
• The difference between the required and arrival times at each input pin is the
slack time (the time we have to spare).
•213

• The zero-slack algorithm - adds delay to each net until the slacks
are zero, as shown in Figure 16.29 (b).
• The netdelays can then be converted to weights or constraints in
the placement.
• Assumed that all the gates on a net switch at the same time so that the
net delay can be placed at the output of the gate driving the net—a
rather poor timing model but the best we can use without any routing
information.
•214

•215

9 The zero-
slack
algorithm.
•(a) The
circuit with
no net delays.
•(b) The zero-
slack
algorithm
adds net
delays •216

• Advantage
• An important point to remember is that adjusting the net weight, even for
every net on a chip, does not theoretically make the placement algorithms any
more complex—we have to deal with the numbers anyway. It does not matter
whether the net weight is 1 or 6.6, for example.
• Disadvantage
• The practical problem, however, is getting the weight information for
each net (usually in the form of timing constraints) from a synthesis tool
or timing verifier.
• These files can easily be hundreds of megabytes in size.
• With the zero-slack algorithm we simplify but overconstrain the problem.
•217

• Solution
• Deal with paths such as the critical path shown in Figure 16.29 (a) and not just
nets .
• Disadvantage of Path-based method
• They are complex and not all commercial tools have this capability
• Path delays between gates can not be predicted with only placement
information.
• Because we are using simple approximations to the total net length (such as
the half-perimeter measure) and then use this to estimate a net delay (the
same to each pin on a net).
• It is not until the routing step that we can make accurate estimates of the
actual interconnect delays.
•218

UNIT IV
ROUTING
Dr.K.Kalyani
AP, ECE,
TCE.
•220

Introduction
 Once the designer has
 Floorplanned a chip
 The logic cells within the flexible blocks have been placed
 Time to make the connections by routing the chip.
 This is still a hard problem that is made easier by dividing it into smaller
problems.
 Routing is usually split into
 Global routing followed by detailed routing .
•221

•The starting point of floorplaning and placement steps for
the viterbi decoder
•-collection of standard cells with no room set aside yet for
routing. •222

The starting point of floorplaning and
placement steps for the viterbi decoder
• Small boxes that look like bricks - outlines of the standard cells.
• Largest standard cells, at the bottom of the display (labeled dfctnb)
- 188 D flipflops.
• '+' symbols -drawing origins of the standard cells—for the D flip-flops
they are shifted to the left and below the logic cell bottom left-hand
corner.
• Large box surrounding all the logic cells - estimated chip size.
• (This is a screen shot from Cadence Cell Ensemble.)
•223

The viterbi decoder after floorplanning
•224

•FIGURE 17.1 The core of the Viterbi decoder chip after placement (a screen shot from
Cadence Cell Ensemble) •225

•FIGURE 17.2 The core of the Viterbi decoder chip after the completion of global and detailed
routing (a screen shot from Cadence Cell Ensemble). This chip uses two-level metal. Although you
cannot see the difference, m1 runs in the horizontal direction and m2 in the vertical direction. •226

Global Routing
• The details of global routing differ slightly between
– cell-based ASICs, gate arrays, and FPGAs, but the principles are the
same.
• A global router does not make any connections, it just plans them.
• Global route the whole chip (or large pieces if it is a large chip) before detail
routing the whole chip (or the pieces).
•227

Goals and Objectives
• Input to routing
– Floorplan that includes the locations of all the fixed and flexible blocks;
– Placement information for flexible blocks;
• Locations of all the logic cells.
• Goal of global routing
– To provide complete instructions to the detailed router on where to
route every net.
• Objectives of global routing
– Minimize the total interconnect length.
– Maximize the probability that the detailed router can complete
the routing.
– Minimize the critical path delay.
•228

Measurement of Interconnect Delay
• After placement, the logic cell positions are fixed and the global router can afford to use
better estimates of the interconnect delay.
• To illustrate one method, we shall use the Elmore constant to estimate the interconnect
delay for the circuit shown in Figure 17.3 .
•FIGURE 17.3 Measuring the delay of a net. (a) A simple circuit with an inverter A driving a
net with a fanout of two. Voltages V 1 , V 2 , V 3 , and V 4 are the voltages at intermediate
points along the net. (b) The layout showing the net segments (pieces of interconnect).
(c) The RC model with each segment replaced by a capacitance and resistance. The ideal
switch and pull-down resistance R pd model the inverter A.
•229

The problem is to find the voltages at the inputs to logic cells B and C taking
into account the parasitic resistance and capacitance of the metal interconnect.
Figure 17.3 (c) models logic cell A as an ideal switch with a pull-down
resistance equal to R pd and models the metal interconnect using resistors and
capacitors for each segment of the interconnect.
•The Elmore constant for node 4 (labeled V 4 ) in the network
shown in Figure 17.3 (c) is
4
ζ 4 = ΣR k 4 C k (17.1)
k = 1
= R 14 C 1 + R 24 C 2 + R 34 C 3 + R 44 C 4 ,
•where,
•230

In Eq. 17.2 notice that R 24 = R pd + R 1 (and not R pd + R 1 + R 2 ) because
R 1 is the resistance to V 0 (ground) shared by node 2 and node 4.
Suppose we have the following parameters (from the generic 0.5 m m CMOS
process, G5) for the layout shown in Figure 17.3 (b):
• m2 resistance is 50 m Ω /square.
• m2 capacitance (for a minimum-width line) is 0.2 pFmm –1 .
• 4X inverter delay is 0.02 ns + 0.5 CLns ( C L is in picofarads).
• Delay is measured using 0.35/0.65 output trip points.
• m2 minimum width is 3 λ = 0.9 µm.
• 1X inverter input capacitance is 0.02 pF (a standard load).
First we need to find the pull-down resistance, Rpd , of the 4X inverter. If we
model the gate with a linear pull-down resistor, Rpd , driving a load CL , the
output waveform is exp – t /( CLRpd ) (normalized to 1V).
The output reaches 63 percent of its final value when t = CLRpd , because
exp (–1) = 0.63. Then,because the delay is measured with a 0.65 trip point, the
constant 0.5 nspF –1 0.5kW is very close to the equivalent pull-down
resistance. Thus, Rpd = 500 Ω .
•231

•232
•m2 resistance is 50 m Ω square.
•m2 capacitance (for a minimum-width
line) is 0.2 pFmm –1 .
•4X inverter delay is 0.02 ns + 0.5 CLns (
C L is in picofarads).
•Delay is measured using 0.35/0.65
output trip points.
•m2 minimum width is 3 λ = 0.9 µm.
•1X inverter input capacitance is 0.02
pF (a standard load).

• R1=R2 = 6 Ω
• R3=56 Ω
• R4=112 Ω
• C 1=0.02 pF
• C 2 =0.04 pF
• C 3=0.2 pF
• C 4=0.42 pF
Now we can calculate the path resistance, Rki, values (notice that Rki = Rki):
R14 = 500 Ω + 6 Ω =506 Ω
R24 = 500 Ω + 6 Ω =506 Ω
R34 =500 Ω + 6 Ω + 56 Ω =562 Ω
R44 =500 Ω + 6 Ω + 56 Ω + 112 Ω =674 Ω (17.5)
•233

Finally, we can calculate Elmore’s constants for node 4 and node 2 as follows:
ζD4 = R 14 C 1 + R 24 C 2 + R 34 C 3 + R 44 C 4 (17.6)
= (506)(0.02) + (506)(0.04)
+ (562)(0.2) + (674)(0.42)
= 425 ps .
ζD2 = R 12 C 1 + R 22 C 2 + R 32 C 3 + R 42 C 4 (17.7)
= ( R pd + R 1 )( C 1 + C 3 + C 4 )
+ ( R pd + R 1 + R 2 ) C 2
= (500 + 6 + 6)(0.04)
+ (500 + 6)(0.02 + 0.2 + 0.2)
= 344 ps .
•and ζD4 – ζD2 = (425 – 344) = 81 ps.
•A lumped-delay model neglects the effects of interconnect
resistance and simply sums all the node capacitances (the
lumped capacitance ) as follows:
• ζD = R pd ( C 1 + C 2 + C 3 + C 4 ) (17.8)
• = (500) (0.02 + 0.04 + 0.2 + 0.42)
•234

Measurement of delay
The delay of the inverter can be assigned as follows:
– 20 ps (the intrinsic delay, 0.02 ns, due to the cell output
capacitance),
– 340 ps (due to the pull-down resistance and the output
capacitance),
– 4 ps (due to the interconnect from A to B), (ζD2- ζD )
– 85 ps (due to the interconnect from A to C) (ζD4- ζD ).
•235

Measurement of Interconnect Delay (contd.,)
• Even using the Elmore constant we still made the following assumptions in
estimating the path delays:
• A step-function waveform drives the net.
• The delay is measured from when the gate input changes.
• The delay is equal to the time constant of an exponential waveform
that approximates the actual output waveform.
• The interconnect is modeled by discrete resistance and capacitance
elements.
• The global router could use more sophisticated estimates that remove some
of these assumptions, but there is a limit to the accuracy with which delay
can be estimated during global routing
• When the global router attempts to minimize interconnect delay, there is
an important difference between a path and a net.
• The path that minimizes the delay between two terminals on a net is not
necessarily the same as the path that minimizes the total path length of
the net.
•236

Global Routing Methods
• Many of the methods used in global routing are based on the solutions to the
tree on a graph problem.
• sequential routing :
One approach to global routing takes each net in turn and calculates
the shortest path using tree on graph algorithms—with the added
restriction of using the available channels.
Disadvantage:
• As a sequential routing algorithm proceeds, some channels will
become more congested since they hold more interconnects than
others.
• In the case of FPGAs and channeled gate arrays, the channels have a
fixed channel capacity and can only hold a certain number of
interconnects.
•237

Global Routing Methods (contd.,)
• There are two different ways that a global router normally handles this problem.
1.Order independent Routing
2.Order dependent Routing
• Order-independent routing, a global router proceeds by routing each net, ignoring
how crowded the channels are. Whether a particular net is processed first or last does
not matter, the channel assignment will be the same.
• Order-independent routing, after all the interconnects are assigned to channels, the
global router returns to those channels that are the most crowded and reassigns some
interconnects to other, less crowded, channels.
• order dependent :A global router can consider the number of interconnects already
placed in various channels as it proceeds. In this case the global routing is order
dependent —the routing is still sequential, but now the order of processing the nets will
affect the results.
• Iterative improvement or simulated annealing may be applied to the solutions found
from both order-dependent and order-independent algorithms.
•238

Global Routing Methods (contd.,)
• Hierarchical routing handles all nets at a particular level at once.
• Rather than handling all of the nets on the chip at the same time, the global-
routing problem is made more tractable by dividing the chip area into levels of
hierarchy.
• By considering only one level of hierarchy at a time the size of the problem is
reduced at each level.
• There are two ways to traverse the levels of hierarchy.
• top-down approach :- Starting at the whole chip, or highest level, and
proceeding down to the logic cells is the.
• The bottom-up approach starts at the lowest level of hierarchy and globally
routes the smallest areas first.
•239

Global Routing
• There are two types of areas to global route:
– between blocks
– inside the flexible blocks
•240

Global Routing Between Blocks
•FIGURE 17.4 Global routing for a cell-based ASIC formulated
as a graph problem. (a) A cell-based ASIC with numbered
channels. (b) The channels form the edges of a graph. (c) The
channel-intersection graph. Each channel corresponds to an
edge on a graph whose weight corresponds to the channel
length. •241

( contd.,)
•FIGURE 17.5 Finding paths in global routing. (a) A cell-based ASIC showing a single net
with a fanout of four (five terminals). We have to order the numbered channels to complete
the interconnect path for terminals A1 through F1. (b) The terminals are projected to the
center of the nearest channel, forming a graph. A minimum-length tree for the net that uses
the channels and takes into account the channel capacities. (c) The minimum-length tree
does not necessarily correspond to minimum delay. If we wish to minimize the delay
from terminal A1 to D1, a different tree might be better. •242

( contd.,)
• Global routing is very similar for cell-based ASICs and gate arrays, but there
is a very important difference between the types of channels in these
ASICs.
• In channeled gate-arrays and FPGAs the size, number, and location of
channels are fixed.
• Advantage - the global router can allocate as many interconnects to each
channel as it likes, since that space is committed anyway.
• Disadvantage - there is a maximum number of interconnects that each
channel can hold.
• If the global router needs more room, even in just one channel on the whole
chip, the designer has to repeat the placement-and-routing steps and try again
(or use a bigger chip).
•243

Global Routing Inside Flexible Blocks
•FIGURE 17.6 Gate-array global routing. (a) A small gate array. (b) An enlarged view of the routing. The
top channel uses three rows of gate-array base cells; the other channels use only one. (c) A further
enlarged view showing how the routing in the channels connects to the logic cells. (d) One of the logic
cells, an inverter. (e) There are seven horizontal wiring tracks available in one row of gate-array base
cells—the channel capacity is thus 7
•244

Global Routing Inside Flexible Blocks (contd.,)
•FIGURE 17.7 The gate-array inverter from Figure 17.6
d. (a) An oxide-isolated gate-array base cell, showing
the diffusion and polysilicon layers. (b) The metal and
contact layers for the inverter in a 2LM (two-level
metal) process. (c) The router’s view of the cell in a 3LM•245

Global Routing Inside Flexible Blocks
FIGURE 17.8 Global routing a gate array. (a) A single global-routing cell (GRC or routing bin) containing 2-by-4
gate-array base cells. For this choice of routing bin the maximum horizontal track capacity is 14, the maximum
vertical track capacity is 12. The routing bin labeled C3 contains three logic cells, two of which have feedthroughs
marked 'f'. This results in the edge capacities shown. (b) A view of the top left-hand corner of the gate array
showing 28 routing bins. The global router uses the edge capacities to find a sequence of routing bins to connect
the nets.
•246

Timing-DrivenMethods
• As in timing-driven placement, there are two main approaches to timing-driven routing:
– net-based and path-based.
• Path-based methods are more sophisticated.
For example, if there is a critical path from logic cell A to B to C, the global router
may increase the delay due to the interconnect between logic cells A and B if it
can reduce the delay between logic cells B and C.
• Placement and global routing tools may or may not use the same algorithm to
estimate net delay. If these tools are from different companies, the algorithms are
probably different.
• The algorithms must be compatible, however. There is no use performing placement to
minimize predicted delay if the global router uses completely different
measurement methods.
• Companies that produce floorplanning and placement tools make sure that the
output is compatible with different routing tools—often to the extent of using different
algorithms to target different routers.
•247

Back-annotation
• The global router can give not just an estimate of the total net
length (which was all we knew at the placement stage), but the
resistance and capacitance of each path in each net. This RC
information is used to calculate net delays.
• Back-annotate this net delay information
– to the synthesis tool for in-place optimization or
– to a timing verifier to make sure there are no timing surprises.
• Differences in timing predictions at this point arise due to the
different ways in which the placement algorithms estimate the
paths and the way the global router actually builds the paths.
•248

Detailed Routing
Goal:
• The goal of detailed routing is to complete all the connections between logic
cells.
Objectives:
• The most common objective is to minimize one or more of the following:
– The total interconnect length and area
– The number of layer changes that the connections have to make
– The delay of critical paths
• Minimizing the number of layer changes corresponds to minimizing the
number of vias that add parasitic resistance and capacitance to a connection.
•249

Measurement of Channel Density
Definition of Local and Global channel density
• Maximum local density of channel is Global density
• Channel density is less than or equal to Channel capacity.
•250

Left-edge algorithm
The left-edge algorithm ( LEA ) is the basis for several routing algorithms [
Hashimoto and Stevens, 1971].
The LEA applies to two-layer channel routing, using one layer for the trunks and the
other layer for the branches.
For example, m1 may be used in the horizontal direction and m2 in the vertical
direction.
The LEA proceeds as follows:
1. Sort the nets according to the leftmost edges of the net’s horizontal
segment.
2. Assign the first net on the list to the first free track.
3. Assign the next net on the list, which will fit, to the track.
4. Repeat this process from step 3 until no more nets will fit in the current
track.
5. Repeat steps 2–4 until all nets have been assigned to tracks.
6. Connect the net segments to the top and bottom of the channel.
•251

Constraints and Routing Graphs
• Two terminals that are in the same column in a channel create a
vertical constraint .
• Overlap between the trunks of nets is called horizontal constraint.
•254

Dog-Leg router
• A dogleg router removes the restriction that each net can use only one
track or trunk.
•255

Area Routing Algorithm- Lee-Maze algorithm
[For general shaped areas]
• Finds a path from source (X) to target (Y) by emitting a wave from both
the source and the target at the same time.
• Successive outward moves are marked in each bin.
• Once the target is reached, the path is found by backtracking (if there is a
choice of bins with equal labeled values, choose the bin that avoids changing
direction). (The original form of the Lee algorithm uses a single wave.)
•256

Hightower or line search-Area routing algorithm
[For general shaped areas]
• 1. Extend lines from both the source and target toward each
other.
•2. When an extended line, known as an escape line , meets
an obstacle, choose a point on the escape line from which to
project another escape line at right angles to the old one. This
point is the escape point .
•257

Special routing- CLK routing
• Gate arrays normally use a clock spine (a regular grid), eliminating the need
for special routing.
• The clock distribution grid is designed at the same time as the gate-array
base to ensure a minimum clock skew and minimum clock latency—given
power dissipation and clock buffer area limitations.
• Cell-based ASICs may use either a clock spine, a clock tree, or a hybrid
approach.
• Figure shows how a clock router may minimize clock skew in a clock spine
by making the path lengths, and thus net delays, to every leaf node equal—
using jogs in the interconnect paths if necessary.
• More sophisticated clock routers perform clocktree synthesis
(automatically choosing the depth and structure of the clock tree) and
clock-buffer insertion (equalizing the delay to the leaf nodes by balancing
interconnect delays and buffer delays).
•258

Special routing- CLK routing
FIGURE: Clock routing. (a) A clock network for the cellbased ASIC
(b) Equalizing the interconnect segments between CLK and all
destinations (by including jogs if necessary) minimizes clock
skew.
•259

Special routing- Power routing
• Power bus width
• Each of the power buses has to be sized according to the current it
will carry.
• Too much current in a power bus can lead to a failure through a
mechanism known as electromigration.
• The required power-bus widths can be estimated automatically
from library information, from a separate power simulation tool, or
by entering the power-bus widths to the routing software by
hand.
• Many routers use a default power-bus width so that it is quite easy
to complete routing of an ASIC without even knowing about this
problem.
•260

• Gate-Array ASIC
• Gate arrays normally use a regular power grid as part of
the gate-array base.
• The gate-array logic cells contain two fixed-width power
buses inside the cell, running horizontally on m1.
• The horizontal m1 power buses are then strapped in a
vertical direction by m2 buses, which run vertically
across the chip.
•261

• Cell-based ASIC
• Standard cells are constructed in a similar fashion to gate-array cells, with
power buses running horizontally in m1 at the top and bottom of each
cell.
• A row of standard cells uses end-cap cells that connect to the VDD and VSS
power buses placed by the power router.
• Power routing of cell-based ASICs may include the option to include
vertical m2 straps at a specified intervals.
• In a three-level metal process, power routing is similar to two-level metal
ASICs. Power buses inside the logic cells are still normally run on m1.
Using HVH routing it would be possible to run the power buses on m3 and
drop vias all the way down to m1 when power is required in the cells. •262

Circuit Extraction
• After detailed routing is complete, the exact length and position of each
interconnect for every net is known.
• Now the parasitic capacitance and resistance associated with each
interconnect, via, and contact can be calculated.
• This data is generated by a circuit-extraction tool in one of the formats.
• standard parasitic format ( SPF )
• The standard parasitic format ( SPF ) describes interconnect delay
and loading due to parasitic resistance and capacitance.
• There are three different forms of SPF:
– Two of them ( regular SPF and reduced SPF ) contain the same
information, but in different formats, and model the behavior of
interconnect;
– Third form of SPF ( detailed SPF ) describes the actual parasitic
•263

Circuit Extraction
• The load at the output of gate A is represented by one of three models: lumped-C,
lumped- RC, or PI segment.
Figure: The regular and reduced standard parasitic format (SPF) models for
interconnect. (a) An example of an interconnect network with fanout. The driving-point
admittance of the interconnect network is Y ( s ). (b) The SPF model of the interconnect.
(c) The lumped-capacitance interconnect model. (d) The lumped-RC interconnect
model. (e) The PI segment interconnect model .
The values of C , R , C 1 , and C 2 are calculated so that Y 1 ( s ), Y 2 ( s ), and Y 3 ( s ) are the
first-, second-, and third-order Taylor-series approximations to Y ( s ).
•264

Circuit Extraction
The key features of regular and reduced SPF are as follows:
• The loading effect of a net as seen by the driving gate is represented by
choosing one of three different RC networks: lumped-C, lumped-RC, or PI
segment (selected when generating the SPF) [ O’Brien and Savarino, 1989].
• The pin-to-pin delays of each path in the net are modeled by a simple RC
delay (one for each path). This can be the Elmore constant for each path, but it
need not be.
• The reduced SPF ( RSPF) contains the same information as regular SPF,
but uses the SPICE format.
• Detailed SPF:
• The detailed SPF ( DSPF) shows the resistance and capacitance of each
segment in a net, again in a SPICE format. There are no models or
assumptions on calculating the net delays in this format.
•265

Design-Rule Check ( DRC )
• ASIC designers perform two major checks before fabrication.
• DRC:
• The first check is a design-rule check ( DRC ) to ensure that nothing
has gone wrong in the process of assembling the logic cells and
routing.
• The DRC may be performed at two levels.
• Phantom-Level DRC:
• The first level of DRC is a phantom-level DRC , which checks for
shorts, spacing violations, or other design-rule problems between
logic cells.
• This is principally a check of the detailed router.
• If the real library-cell layouts (sometimes called hard layout ) can be
accessed, we can instantiate the phantom cells and perform a
second-level DRC at the transistor level.
•266

• Dracula check:
• This is principally a check of the correctness of the library cells.
• Normally the ASIC vendor will perform this check using its own
software as a type of incoming inspection.
• The Cadence Dracula software is one de facto standard in this area,
and you will often hear reference to a Dracula deck that consists of
the Dracula code describing an ASIC vendor’s design rules.
• Sometimes ASIC vendors will give their Dracula decks to customers so
that the customers can perform the DRCs themselves.
•267

• Layout Vs Schematic check:
• To ensure that what is about to be committed to silicon
is what is really wanted.
• An electrical schematic is extracted from the physical
layout and compared to the netlist.
• This closes a loop between the logical and physical design
processes and ensures that both are the same.
• The LVS check is not as straightforward as it may sound,
however. •268

• Problems in LVS check:
• The first problem is transistor-level netlist for a large ASIC forms an
enormous graph.
• LVS software essentially has to match this graph against a reference
graph that describes the design.
• Ensuring that every node corresponds exactly to a corresponding
element in the schematic (or HDL code) is a very difficult task.
• The first step is normally to match certain key nodes (such as the
power supplies, inputs, and outputs), but the process can very quickly
become bogged down in the thousands of mismatch errors that are
inevitably generated initially.
•269

• Problems in LVS check:
• The second problem with an LVS check is creating a true reference.
• The starting point may be HDL code or a schematic.
• Logic synthesis, test insertion, clock-tree synthesis, logical-to-physical
pad mapping, and several other design steps each modify the
netlist.
• The reference netlist may not be what we wish to fabricate.
• In this case designers increasingly resort to formal verification that
extracts a Boolean description of the function of the layout and
compare that to a known good HDL description.
•270

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