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ARMicrocontroller Memory and Exceptions,Traps.ppt
- 1. Objectives • To learn about CISC and RISC systems • To familiarize with the Memory System in ARM • Define ARM exceptions and handling
- 2. Introduction -CISC and RISC CISC Single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) capable of multi-step operations or addressing modes within single instructions RISC Uses simple instructions that can be divided into multiple instructions which perform low-level operation within single clock cycle
- 3. CISC Approach :- The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. A CISC processor would come prepared with a specific instruction “MULT”. When executed, this instruction 1.Loads the two values into separate registers 2.Multiplies the operands in the execution unit 3.And finally third, stores the product in the appropriate register. Multiplying two numbers A = A * B; Example
- 4. Thus, the entire task of multiplying two numbers can be completed with one instruction MULT A,B MULT is what is known as a “complex instruction.” It operates directly on the computer’s memory banks and does not require the programmer to explicitly call any loading or storing functions. Advantage:- 1.Compiler has to do very little work to translate a high-level language statement into assembly 2.Length of the code is relatively short 3.Very little RAM is required to store instructions 4.The emphasis is put on building complex instructions directly into the hardware. CISC Approach
- 5. Use simple instructions that can be executed within one clock cycle. Thus, the “MULT” command described above could be divided into three separate commands: 1.“LOAD” which moves data from the memory bank to a register 2.“PROD” which finds the product of two operands located within the registers 3.“STORE” which moves data from a register to the memory banks. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly: LOAD R1, A <<<======this is assembly statement LOAD R2,B <<<======this is assembly statement PROD A, B <<<======this is assembly statement STORE R3, A <<<======this is assembly statement RISC Approach
- 6. RISC Operation • More lines of code, more RAM is needed to store the assembly level instructions. • The compiler must also perform more work to convert a high-level language statement into code of this form. • Advantage:- 1. Each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle “MULT” command.
- 7. RISC 2.These RISC “reduced instructions” require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock) 3.Pipelining is possible.
- 8. Load-Store Mechanism • LOAD/STORE mechanism:- Separating the “LOAD” and “STORE” instructions actually reduces the amount of work that the computer must perform. • After a CISC-style “MULT” command is executed, the processor automatically erases the registers. • If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. • In RISC, the operand will remain in the register until another value is loaded in its place. Example of RISC & CISC CISC instruction set architectures - PDP-11, VAX, Motorola 68k, and your desktop PCs on intel’s x86 architecture based too . RISC families include DEC Alpha, AMD 29k, ARC, Atmel AVR, Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA- RISC, Power (including PowerPC), SuperH, SPARC and ARM too.
- 9. CISC RISC Emphasis on hardware Emphasis on software Includes multi-clock Single-clock complex instructions reduced instruction only Memory-to-memory: “LOAD” and “STORE” incorporated in instructions Register to register: “LOAD” and “STORE” are independent instructions high cycles per second, Small code sizes Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers CISC and RISC
- 10. Supervisor mode • Protected mode • Ensures that the user code cannot gain supervisor previleges without application checks being carried out • Ensures that the code is not attempting illegal operations • For user level programs system level functions can be accessed through specified supervisor calls – Access to hardware peripheral registers – Character input and output
- 11. ARM Memory System half-word4 word16 0 1 2 3 4 5 6 7 8 9 10 11 byte0 byte 12 13 14 15 16 17 18 19 20 21 22 23 byte1 byte2 half-word14 byte3 byte6 address bit 31 bit 0 half-word12 word8 Address bus: 32 bits 1 word = 32 bits Memory – viewed as a linear array of bytes numbered 0 to 2^(32-1) Data Items may be 8 bit bytes, 16 bit HW or 32 bit words Words always aligned on 4-byte boundaries Each byte location has a unique number. A byte may occupy any of these locations. Word sized data items must occupy a group of 4 byte locations starting at a byte address which is a multiple of 4
- 12. Exceptions • Programming techniques for dealing with error conditions without terminating execution of the program • Changes the normal flow of execution • Fault/trap/abort • Example: – Overflow – Breakpoint – Co-processor not available – Divide by zero – Invalid opcode
- 13. Vector Table Exception Handling • When an exception occurs, the ARM: – Copies CPSR into SPSR_<mode> – Sets appropriate CPSR bits • Change to ARM state • Change to exception mode • Disable interrupts (if appropriate) – Stores the return address in LR_<mode> – Sets PC to vector address • To return, exception handler needs to: – Restore CPSR from SPSR_<mode> – Restore PC from LR_<mode> This can only be done in ARM state. Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00
- 14. Exception handling PC r14_exc CPSR SPSR_exc Change operating mode To application exception mode PC 00 to 1C H(vector address) – exception handler Exception handler uses r13_exc (Dedicated stack in mem to save some registers for use as work registers Restore User registers PC, CPSR Adjust PC value saved in R14_exc to compensate for pipeline state when Exception arose On Interrupt On return
- 15. Summary • Example instruction execution in CISC and RISC studies • ARM memory system and Expection handling in ARM explained
- 16. References • Marilyn Wolf, Computers as Components: Principles of Embedded Computing System Design, Morgan Kaufmann Publishers, Third Edition, 2012 • Steve Furber, ARM SOC Architecture II Edition Pearson 2011