Verification of Graphics ASICs (Part I)
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This document appears to be a presentation given by AMD on verification challenges for graphics ASICs. The presentation covers an overview of AMD, GPU systems, 3D graphics basics, and verification challenges. It discusses the size and complexity of GPUs, layered code and testbenches used for verification, and the use of hardware emulation and functional coverage.
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Verification Automation Using IPXACTDVClub This document discusses using the IP-XACT standard to address challenges in verification automation. IP-XACT allows generating verification platforms, register tests, and other elements from a single IP description. It standardizes IP information exchange and reduces duplication. Using IP-XACT, a verification flow is proposed where the testbench, models, and register tests are automatically generated from an IP-XACT file, improving consistency and reducing turnaround times. IP-XACT is now an IEEE standard developed by the SPIRIT consortium to describe IPs in a vendor-neutral way and enable maximum automation.
Validation and Design in a Small Team Environment
Validation and Design in a Small Team EnvironmentDVClub The document discusses validation and design in small teams with limited resources. It proposes constraining designs to a single clock rate, standardized interfaces, and automated test cases to streamline verification. This reduces complexity and verification costs, allowing designs to be completed more quickly despite limited experience. Standardizing interfaces and separating algorithm from implementation verification improves efficiency enough to overcome typical verification to design ratios.
Trends in Mixed Signal Validation
Trends in Mixed Signal ValidationDVClub This document discusses trends in mixed signal validation. It begins with an overview of mixed signal systems that contain both analog and digital components. The evolution of mixed signal validation is then described, from early approaches that simulated analog and digital components separately to modern tools that can jointly simulate both domains using languages like Verilog-AMS. The key steps in mixed signal validation are outlined, including modeling components in Verilog-AMS, validating blocks, and performing system-level validation. Throughout, the importance of accurate models for verification is emphasized. Examples of mixed signal modeling and a charge pump PLL validation environment are also provided.
Verification In A Global Design Community
Verification In A Global Design CommunityDVClub Verification teams at chip design companies now work globally, presenting communication challenges. Time zone differences make real-time collaboration difficult, and documentation through tools like TWiki can suffer if not well-organized. However, global teams also provide benefits by making more people and creative ideas available. Companies like AMD are addressing these issues through centers of expertise that standardize methodologies, tools, and components to facilitate collaboration across sites, while still allowing projects flexibility and innovation. Regular reviews help continuously improve processes as new techniques are adopted or abandoned.
Design Verification Using SystemC
Design Verification Using SystemCDVClub Greg Tierney of Avid presented on their experiences using SystemC for design verification. Some key points:
1) Avid chose SystemC to enhance their existing C++ verification code and take advantage of its built-in verification capabilities like randomization and multi-threading.
2) SystemC helped Avid solve problems like connecting entire HDL modules to their testbench and monitoring foreign signals.
3) While SystemC provided benefits, Avid also encountered issues with its compile/link performance and large library size. Overall, Avid found SystemC reliable for design verification over three years of use.
Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressDVClub This document provides an overview of the verification strategy for PCI-Express. It discusses the PCI-Express protocol, including the physical, data link, transaction, and software layers. It outlines the verification paradigm, including functional verification using constrained random testing, assertions, asynchronous/power domain simulations, and performance verification. It also discusses compliance verification through electrical, data link, transaction, and system architecture checklists. Finally, it discusses design for verification through a modular and scalable architecture to promote reusability and reduce verification effort and complexity.
SystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification ProcessDVClub 1) Visual SVA tools like Zazz allow designers to create complex SystemVerilog assertions through a graphical interface, addressing issues with SVA syntax.
2) Zazz also enables debugging assertions as they are created by generating constrained random tests, improving assertion quality before use in verification.
3) Using assertions improved the author's verification and debugging process, identifying errors sooner and in corner cases, and provided additional value to IP customers through early fault detection.
OpenSPARC T1 Processor
OpenSPARC T1 ProcessorDVClub The document discusses Sun Microsystems' UltraSPARC T1 processor. It provides an overview of the processor's features, including its implementation of chip multi-threading with up to 8 cores and 32 threads. It describes the processor's design choices such as shared caches and memory controllers. It also discusses Sun's strategy for verifying the processor's architecture and microarchitecture through directed testing, coverage metrics, and other techniques. Finally, it notes some of the benefits of chip multi-threading for performance, cost, reliability, and power efficiency.
Using Assertions in AMS Verification
Using Assertions in AMS VerificationDVClub This document discusses using assertions in analog mixed-signal (AMS) verification. It describes how assertions can be used to check interface assumptions, power mode transitions, and timing relationships for AMS blocks. Assertions provide compact and precise checks that can be reused across different verification methodologies. The document also provides an example of using Verilog-AMS monitors to digitize continuous signals from an AMS model so they can be checked using SystemVerilog assertions.
Low-Power Design and Verification
Low-Power Design and VerificationDVClub This document discusses challenges and requirements for low-power design and verification. It begins with an overview of how leakage is significantly increasing due to process scaling and how active power is now a major portion of power budgets. New strategies are needed to address process variations and enhance scaling approaches. The verification flows must support multi-voltage domain analysis and rule-based checking across voltage states while capturing island ordering and microarchitecture sequence errors. Low-power implementation introduces challenges for design representation, implementation across tools, and verification. Methodologies and design flows must be adapted to account for power and ground nets becoming functional signals.
UVM Update: Register Package
UVM Update: Register PackageDVClub The document discusses the UVM register model, which provides an object-oriented shadow model for registers and memories in a DUT. It includes components like fields, registers, register files, memory, and blocks. The register model allows verification of register access and provides a standardized way to build reusable verification components.
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...DVClub This document discusses the verification of Freescale's QorIQ Communication Platform, which contains the new CoreNet fabric. It outlines the verification challenges, methodology used, and SystemVerilog verification IP (VIP) created. The methodology employed a transaction-based approach with hierarchical verification and extensive reuse. SystemVerilog VIP was developed for the CoreNet fabric and other components. This included object-oriented models, monitors, coverage, and stimulus. The verification was successful in validating the CoreNet platform early using SystemVerilog.
Verification of Wireless SoCs: No Longer in the Dark Ages
Verification of Wireless SoCs: No Longer in the Dark AgesDVClub This document discusses the challenges of verifying wireless system-on-chips (SoCs). It notes that today's highly integrated wireless devices contain multiple processors, modems, multimedia components, and peripherals. Verifying the interactions between these heterogeneous elements and ensuring interoperability is difficult. The document outlines how traditional "golden vector" verification is limited and advocates for modern model-based approaches using constraints, assertions, and directed random testing. It also discusses how power management adds further complexity to verification and requires new methodologies. In summary, verifying today's complex wireless SoCs is challenging but critical to ensure functionality.
I Never Thought I Would Grow Up to be This Formal
I Never Thought I Would Grow Up to be This FormalDVClub This document provides an overview of formal verification from the perspective of an engineer with experience using formal verification tools over time. It defines formal verification and how it differs from simulation-based verification. It then discusses the author's experiences with formal verification from the 1990s to present day, noting how formal verification has become more usable, integrated with design flows, and adopted by more designers. The document also outlines observed benefits of formal verification and common challenges with adopting it. It concludes by predicting continued growth in capacity, capabilities, and adoption of formal verification methods.
OMAP Verification
OMAP VerificationDVClub Verification and validation of OMAP chips is a large, complex process that involves verifying modules, subsystems, and the full chip. It utilizes a strict methodology with defined verification plans, reviews, and metrics to help ensure functionality is thoroughly tested across all levels from RTL to silicon. Automation, reuse, and collaboration across teams are important aspects that help make the process feasible given its size and resources required.
Roy aeroVerifying Power Domains in AeroFONE
Roy aeroVerifying Power Domains in AeroFONEDVClub This document discusses power domain verification for the AeroFONE® chip. It describes the chip's multiple power domains, voltage regulators, and power control feedback loop. Static and dynamic verification methods are used, including specifying power domains, designing interface cells between domains, and modeling the effects of power states and regulator behavior. Dynamic verification exercises all possible power up sequences and mode transitions using assertions to check for valid system power states.
Challenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelDVClub This document discusses challenges in using the Universal Verification Methodology (UVM) at the system-on-chip (SoC) level and proposes solutions. It outlines key features of UVM, then describes challenges like lack of control over UVM verification components from C code and difficulty reusing test cases across different levels. The document proposes a wrapper to connect UVM and SystemC ports and adds a TLM export and register-controlled sequence to allow processor control over sequences. It demonstrates controlling a sequence from a processor through this interface. Finally, it discusses areas like seamless UVM-SystemC connections that could be improved in future UVM versions.
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Verification of Graphics ASICs (Part I)
- 1. DV Club Westford MA Verification of Graphics ASICs Shaw Yang Gary Greenstein AMD Marlborough MA May 28, 2008
- 2. AMD: DV Club - Westford MA2 May 30, 2008 Agenda AMD Overview GPU Systems Overview 3D Graphics Basics Pretty Pictures Verification Challenges Size and complexity Layered CODE and Testbenches HW Emulation Functional Coverage
- 3. AMD: DV Club - Westford MA3 May 30, 2008 AMD Overview
- 4. AMD: DV Club - Westford MA4 May 30, 20084 New form factors Emerging market opportunities and convergence - x86 Across all the screens of your life AMD Leading the Way May 7, 20084
- 5. AMD: DV Club - Westford MA5 May 30, 2008 The Graphics Market
- 6. AMD: DV Club - Westford MA6 May 30, 2008 Today’s AMD: Capabilities Segments Geography Strengths Customers/Pa rtners Products Tech MFG Cadence Rapid System Level Verification TechTorial6 Blending world-class knowledge, cultures and people Server Workstation Desktop Game Notebook DTV Handheld consoles Greater Latin Europe North Korea Japan China America America Distribution PC OEM Retail Digital ODM Consumer Handheld Media Microprocessors Customer Best-in- Chipset Graphics & Media Focus Class Products Processors 64-bit Multi- Hyper- Tech-Centric CrossFire Avivo Low H.264 Core Transport Culture Power Fabs and Process Technology Foundry Partnerships
- 7. AMD: DV Club - Westford MA7 May 30, 2008 Transform Processing Technology CPU Drivers BIOS Media Centric Graphics Centric Data Centric General Purpose Platforms GPUChipset Drivers BIOS Drivers BIOS
- 8. AMD: DV Club - Westford MA8 May 30, 2008 GPU System Overview
- 9. AMD: DV Club - Westford MA9 May 30, 2008 GPU in PC System – Discrete Graphics AGP / PCI Express ToDisplay Graphics Memory System Memory RS690 SB700
- 10. AMD: DV Club - Westford MA10 May 30, 2008 GPU in PC System – Integrated Graphics To Display AGP / PCI Express Graphics Memory System Memory RS690G SB700
- 11. AMD: DV Club - Westford MA11 May 30, 2008 GPU in Desktop System PC Chassis Integrated Graphics
- 12. AMD: DV Club - Westford MA12 May 30, 2008 GPU in Notebook System Integrated Graphics Discrete Graphics
- 13. AMD: DV Club - Westford MA13 May 30, 2008 3D Graphics Basics
- 14. AMD: DV Club - Westford MA14 May 30, 2008 Computerized Graphics
- 15. AMD: DV Club - Westford MA15 May 30, 2008 The Digital World
- 16. AMD: DV Club - Westford MA16 May 30, 2008 Vertexes, Polygons and Pixels Vertex 1 Vertex 2 Vertex 3 Triangle Mesh Wire Frame
- 17. AMD: DV Club - Westford MA17 May 30, 2008 Creating the Objects – Vertexes Vertexes
- 18. AMD: DV Club - Westford MA18 May 30, 2008 Creating the Objects – Polygons Object Geometry
- 19. AMD: DV Club - Westford MA19 May 30, 2008 Scan Conversion Conversion from triangles to pixels Break up triangles into raster elements (pixels) Prepare them for per-fragment processing Scan line
- 20. AMD: DV Club - Westford MA20 May 30, 2008 Creating the Objects – Pixels
- 21. AMD: DV Club - Westford MA21 May 30, 2008 Creating the Objects – Textures Texture