Manual cpu clocking system
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The document describes the clocking system options for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 microcontrollers. It discusses the seven clock sources including fast RC oscillator, primary oscillator using crystals or external clock, and low-power RC oscillator. It explains how to select a clock source using configuration bits and how to enable clock switching between sources at runtime. It also describes using the on-chip PLL to multiply the oscillator frequencies and generate higher system clock speeds. The Fail-Safe Clock Monitor is discussed which allows the device to switch to a backup clock source if the primary oscillator fails.
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Manual cpu clocking system
- 1. CPU Clocking System The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices provide seven system clock options: Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator Low-Power RC (LPRC) Oscillator FRC Oscillator with postscaler Fast RC The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> bits (CLKDIV<10:8>). Primary The primary oscillator can use one of the following as its clock source: XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins. EC (External Clock): The external clock signal is directly applied to the OSC1 pin. Low-Power RC The LPRC (Low-Power RC) internal oscIllator runs at a nominal frequencyof32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). FRC The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase Locked Loop (PLL) to provide a wide range of output frequencies for device operation. PLL configuration is described in Section 8.1.3 “PLL Configuration”. The FRC frequency depends on the FRC accuracy (see Table 24-18) and the value of the FRC Oscillator Tuning register (see Register 8-4).
- 3. 8.1.2 SYSTEM CLOCK SELECTION The oscillator source used ata device Power-on Resetevent is selected using Configuration bit settings. The oscillator Configuration bitsettings are located in the Configuration registers in the program memory. (Refer to Section 21.1 “Configuration Bits” for further details.) The Initial Oscillator Selection Configuration bits,FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits,POSCMD<1:0> (FOSC<1:0>), selectthe oscillator source thatis used ata Power-on Reset.The FRC primaryoscillator is the default(unprogrammed) selection. The Configuration bits allow users to choose among 12 differentclock modes,shown in Table 8-1. The output of the oscillator (or the output of the PLL if a PLL mode has been selected) FOSC is divided by 2 to generate the device instruction clock (FCY) and the peripheral clock time base (FP). FCY defines the operating speed of the device, and speeds up to 40MHz are supported bythe dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture. Instruction execution speed or device operating frequency, FCY, is given by: 8.1.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 8-2. The output of the primary oscillator or FRC, denoted as ‘FIN’, is divided down by a prescale factor (N1) of 2, 3,... or 33 before being provided to the PLL’s Voltage Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The prescale factor ‘N1’ is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). The PLL Feedback Divisor,selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M’, by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. The VCO output is further divided by a postscale factor ‘N2.’ This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by: For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed.
- 4. If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultantdevice operating speed is 80/2 = 40 MIPS.
- 5. Programando en el DSPIC Configuraciondel osciladorinternoconDSPIC Utilizando la ecuacion: 𝐹𝑜𝑠𝑐 = 𝐹𝐼𝑁 ∗ ( 𝑀 𝑁1 ∗ 𝑁2 ) 𝐹𝑜𝑠𝑐 = 7.37 MHz.∗ ( 43 2 ∗ 2 ) 𝐹𝑐𝑦 = ( 79.2275 2 ) 𝐹𝑐𝑦 = 39.61375 Este 𝐹𝑐𝑦 se declara en la programación: 8.2 Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have a safeguard lock built into the switch process. 8.2.1 ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to ‘0’. (Refer to Section 21.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bitis unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled.
- 6. This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled.It is held at ‘0’ at all times. 8.2.2 OSCILLATOR SWITCHING SEQUENCE Performing a clock switch requires this basic sequence: 1. If desired, read the COSC bits (OSCCON<14:12>) to determine the current oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. 4. Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits.If they are the same,the clock switch is a redundantoperation.In this case,the OSWEN bit is cleared automatically and the clock switch is aborted. 2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status bits are cleared. 3. The new oscillator is turned on by the hardware ifit is not currently running.If a crystal oscillator mustbe turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is using the PLL, the hardware waits until a PLL lock is detected (LOCK = 1). 4. The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC status bits. 6. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). 8.3 Fail-Safe Clock Monitor (FSCM) The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. In the event of an oscillator failure,the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator.Then the application program can either attemptto restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector.
- 7. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. EN LA PAGINA 126 DEL DATASHEET EXPLICA ESTE CODIGO: