LOGIC LEVEL PPT.pptx on low power vlsi design

PRESENTATION
LOW POWER VLSI DESIGN
Logic Level Techniques
Presented By
MUSKAN.S

CONTENTS
Gate Reorganization
Signal Gating
Logic Encoding
State machine Encoding
Precomputation Logic
2

Logic Design
 Logic design was once the primary abstraction level where automatic design
synthesis begins
 The most prevalent theme in logic level power optimization techniques is the
reduction of switching activities
 Switching activities directly contribute to the charging and discharging
capacitance and the short circuit power
 Some switching activities are the result of unspecified or undefined behavior of
a logic system that are not related to its power operation
 Such stray switching activities should be eliminated or reduced if possible
 However, suppressing unnecessary activities usually requires additional
hardware logic that increases the area and consumes power

Gate Reorganization
 Gate reorganization is applied to gate level network to preduce logically
equivalent networks with different qualities for power, area, and delay.
 The complexity of the gate reorganization problem limits manual solution to
small circuits only.
 Gate level reorganization is a central operation of logic synthesis.
 Most gate reorganization tasks are performed by automated software in the
logic synthesis system

Local Restructuring
 Gate reorganization is an operation to transform one logic circuit to another that
is functionally equivalent
 Logic restructuring techniques use local restructuring rules to transform one
network to another
 Some basic transformation operators are:
1. Combine several gates into a single gate
2. Decompose a single gate into several gates
3. Duplicate a gate and redistribute its output connections
4. Delete a wire
5. Add a wire
6. Eliminate unconnected gates

Local transformation Operators for gate reorganization
Local Restructuring
Fig1. Local transformation operators for gate reorganization

Local transformation Operators for gate reorganization
Local Restructuring
Fig2. Local transformation operators for gate reorganization

Local Restructuring
 COMBINE operator can be used to hide high frequency nodes inside a
cell
so that the node capacitance is not being switched
 DECOMPOSE and DUPLICATE operators help to separate the critical path
from the non critical ones so that the latter can be sized down
 DELETE WIRE operator reduces the circuit size
 ADD WIRE operator helps to provide an intermediate circuit that may
eventually lead to a better one

Signal Gating
 Signal gating refers to a class of general techniques to mask unwanted
switching activities from propagating forward, causing unnecessary power
dissipation
 The probabilistic techniques are often used for switching activity analysis
 The simplest method to implement signal gating is to put an AND/OR gate at
the signal path to stop the propagation of the signal when it needs to be
masked
 Another method is to use a latch or flip flop to block the propagation of the
signal
 Sometimes a transmission gate or tristate buffer can be used in place of a latch
if charge leakage is not a concern
 The various logic implementation of signal gating is shown below

Signal Gating
Fig3. Various logic signal implementation of signal gating
 The signals at the bottom of the circuits are control signals used to suppress
the source signal on the left from propagating to the gated signal on the right
 Control signal frequency must be low

Logic Encoding
 The logic designer of a digital circuit often has the freedom of choosing a
different encoding scheme as long as the functional specification of the circuit
is met
 For e.g. an 8 bit counter can be implemented using the binary counting
sequence or the gray code sequence
 Different encoding implementation often lead to different power, area and delay
tradeoff
 The encoding techniques require the knowledge of signal statistics in order to
make design decisions

Binary versus Gray Code Counting
 Consider two n-bit counters implemented with Binary and Gray code counting
sequences
 The counting sequences of the two counters are shown in Table1
 Toggle activities of Binary versus Gray counter are shown in Table2
Table1 Table2

Binary versus Gray Code Counting
 When n is large, the Binary counter has twice as many transitions as the Gray
counter
 Since the power dissipation is related to toggle activities, a Gray counter is
generally more power efficient than a Binary counter

Bus Invert Encoding
 Bus invert encoding is a low power encoding technique that is suitable for a set
of parallel synchronous signals e.g.: off-chip busses
 At each clock cycle, the data sender examines the current and next values of
the bus and decides whether sending the true or the compliment signal leads
to fewer toggles
 Since the data signals on the bus may be complemented, an additional polarity
signals is sent to the bus receiver to decode the bus data properly

Bus Invert Encoding Example
Example: Eight bit bus
00001100 → 10001101 has Two transitions.
00001100 → 10001101 (DH =2) Polarity Bit =0
10001101 → 01110001
10001101 → 01110001 (DH =6) Polarity Bit =1
Now bits of second pattern are inverted, then instead 01110001 →
10001110 Tx 10001110 will have only TWO transition

Bus Invert Encoding
 Encode N-bit string using N+1bits.
 Compute hamming Distance DH
 DH>N/2: Set Polarity Bit=1 ( Invert Next data valve)
otherwise Polarity bit=0 (Next data value)
Fig4. Architecture of bus invert encoding

Bus Invert Encoding
 The maximum number of toggeling bits of the inverted bus is reduced from n to
n/2
 The assertion of the polarity signal tells the receiver to invert the received bus
signals

Bus Invert Encoding
 We assume that each bit of the bus has the uniform random probability
distribution and is uncorrelated in time.
 This means that the current value of the bus is independent of its previous
values and all bits are mutually uncorrelated.
 The probability of a k-bit transition on an n-bit regular bus is
𝑃𝑘 = 1
2𝑛
𝑛 !
𝑛−𝑘 !𝑘!
The expected number of transitions E [P] of the regular bus is thus

Bus Invert Encoding
 In the bus invert scheme, additional one polarity bit to the bus.
 For the (n + I)-bit inverted bus, the number of bit transitions at any given clock cycle is
never more than n/2.
At each clock cycle, if there is a k-bit transition on the inverted bus, one of the
following two conditions must occur:
1.The polarity bit does not toggle: the probability of this condition is identical to that
of a k-bit transition on a regular bus Pk.
2.The polarity bit toggles: this means that there are k - 1 bit transitions in the
inverted bus, which implies that there are n - k + 1 bit transitions in the corresponding
regular bus. This probability is given by P(n - k + 1)
·
𝑃
1 𝑛!
(𝑛 − 𝑘 + 1) = 2𝑛
𝑛−𝑛+𝑘−1 !(𝑛−𝑘+1)! )
= 1
2𝑛
𝑛 !
𝑘−1 !(𝑛−𝑘+1)!
=P(k-1)

Bus Invert Encoding
 Thus, the probability of a k-bit transition on the (n + I) -bit inverted bus is
The expected number of transitions E [Q] on an inverted bus is thus

Bus Invert Encoding
Table3. Efficiency of bus invert encoding under uniform random signal
The design decision to apply bus invert technique is dependent on signal statistics and the overhead associated with
the polarity decision logic, the polarity signal and the invert/pass gates.

State Machine Encoding
 A state machine is an abstract computation model that can be readily
implemented using Boolean logic and flip flops
 In logic synthesis environment, a state transition graph is specified by the
designer and the synthesis system will produce a gate level circuit based on
the machines specification
 The state transition graph is a functional description of a machine specifying
the inputs and outputs of the machine under a particular state and its
transition to the next state
Fig5. Hardware architecture
of synchronous machine

 The very first step of a state machine synthesis process is to allocate the
state register and assign binary codes to represent the symbolic states. This
process is called the encoding of a state machine
 The encoding of a state machine is one of the most important factors that
determine the quality (area, power, speed etc) of the gate level circuit
 Transition Analysis of State Encoding
 The key parameter to the power efficiency of state encoding is the
expected number of bit transitions E[M] in the state register
 Another parameter is the expected number of transitions of output signals

The very first step of a state machine synthesis process is to allocate the state
register and assign binary codes to represent the symbolic states. This process
is called the encoding of a state machine
The encoding of a state machine is one of the most important factors that
determine the quality (area, power, speed etc) of the gate level circuit
Transition Analysis of State Encoding
The key parameter to the power efficiency of state encoding is the expected
number of bit transitions E[M] in the state register
Another parameter is the expected number of transitions of output signals

Fig6. Functionally identical machines with different encoding

 The expected number of state bit transitions E[M] is given by the sum of
products of edge probabilities and their associated number of bit flips as
dictated by the encoding
 However, a state encoding with the lowest E[M] may not be the one that
results in the lowest overall power dissipation
 The reason is that the particular encoding may require more gates in the
combinational logic, resulting in more signal transitions and power
 The synthesized area and power dissipation of some randomly encoded state
machines is shown below

Fig7. Effect of state encoding on synthesized area and power dissipation

 Precomputation logic optimization is a method to trade area for power in a
synchronous digital circuit
 The principle of precomputation logic is to identify logical conditions at some
inputs to a combinational logic that is invariant to the output
 Since those input values do not affect the output, the input transitions can be
disabled to reduce switching activities
 One variant of precomputation logic is shown below
 Let R1 and R2 are registers with a common clock feeding a combinational
logic circuit with a known Boolean function f(x)
 Due to the nature of the function f(x), there may be some conditions under
which the output of f(x) is independent of the logic value of R2

Fig8. A variant of precomputation logic

 Under such conditions, we can disable the register loading of R2 to avoid
causing unnecessary switching activities, thus conserving power
 The Boolean function f(x) is correctly computed because it receives all
required values from R1
 To generate the load disable signal to R2, a precomputation Boolean function
g(x) is required to detect the condition at which f(x) is independent of R2
 g(x) depends on the input signals of R1 only because the load disable
condition is independent t of R2, otherwise f(x) will depend on the inputs of R2
when the load disable signal is active
 Assuming uncorrelated input bits with uniform random probabilities where
every bit has an equal probability of 0 or 1

 There is 50% probability that An Å Bn = 1 and the register R2 is disabled in
50% of the clock cycles
 Therefore, with only one additional 2 input XOR gate, we have reduced the
signal switching activities of the 2n-2 least significant bits at R2 to half of its
original expected switching frequency
Fig9. Binary comparator function using precomputation logic

 Also, when the load disable signal is asserted, the combinational logic of
the comparator has fewer switching activities because the outputs of R2
are not switched
 The extra power required to compute An Å Bn is negligible compared
to the
power saving even for moderate size of n

 Prior knowledge of the input signal statistics to apply the
precomputation logic technique.
 In comparator design, if the probability of AnBn is close to zero, the
precomputation logic circuit may be inferior, in power and area,
compared to direct implementation.
 Experimental results [5.16] have shown up to 75% power reduction with
an average of 3% area overhead and 1 to 5 additional gate-delay in the
worst-case delay path.

Precomputation Condition
 Given f(X), R I and R2, there is a systematic method to derive a precomputation
function g(X).
Let f(p1, p2, p3, p4, ... , pm, x1, x2, x3, ... , xn) be the Boolean function
Where
p1...pm the precomputed inputs corresponding to RI
x1,...xn are the gated inputs corresponding to R2.
Let fxi be the Boolean function obtained by substituting Xi = 1

Alternate Precomputation Logic
 The precomputation scheme based on Shannon's decomposition is states that
a Boolean function f(x1,…,xn) can be decomposed with respect to the variable
xi as follows:
 The equation allows us to use xi as the load disable signal

 When xi= 0 (xi= 1)the inputs to the logic block fxi can be disabled
 The multiplexer selects the output of the combinational logic block
active
that is
 This means that only one combinational logic block is activated at any clock
cycle
 Power saving is saving is achieved if each of the two decomposed logic
blocks consumes less power than a direct implementation
 However, the precomputation architecture consumes more area and delay in
general
 The latch based precomputation architecture is shown below

Fig10. A precomputation architecture based on Shannon's decomposition
 This architecture is also called guarded evaluation because some inputs to
the logic block C2 are isolated when the signals are not required, to avoid
unnecessary transition

Fig11. A latch-based precomputation architecture
 Transmission gates may be used in place of the latches if the charge storage
and noise immunity conditions permit

Design issues in Precomputation Logic Techniques
 The basic design steps with precomputation logic are as follows:
1. Select precomputation architecture
2. Determine the precomputed inputs R1 and gated inputs R2 given the
function f(x)
3. With R1 and R2 selected, find a precomputation logic function g(x)
4. Note that g(x) is not unique and the choice greatly affects the power efficiency.
The function g(x) may also fail to exist for poor choices of R1 and R2
5. Evaluate the probability of precomputation condition and the potential power
savings. Make sure that the final circuit is not overwhelmed by the additional
logic circuitry and power consumption required to compute g(x)

Design issues in Precomputation Logic
Techniques
 After R1, R2 and g(x) are determined, the precomputation logic can be
synthesized using a logic synthesis tool
 Precomputation by definition is creating redundant logic
 The logic circuit that performs precomputation generally pose difficulties in testing

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