lecture 1 layout presentation of very large scale integration in digital electronics

Introduction to
CMOS VLSI
Design
Circuits & Layout

Circuits and Layout Slide 2
CMOS VLSI Design
Outline
 CMOS Gate Design
 Pass Transistors
 CMOS Latches & Flip-Flops
 Standard Cell Layouts
 Stick Diagrams

CMOS VLSI Design
CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NAND gate

CMOS VLSI Design
CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
D
Y

CMOS VLSI Design
Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
– a.k.a. static CMOS
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)

CMOS VLSI Design
Series and Parallel
 nMOS: 1 = ON
 pMOS: 0 = ON
 Series: both must be ON
 Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
1
1 0 1
a
b
0 0
a
b
0
a
b
1
a
b
1
1 0 1
a
b
g1 g2

CMOS VLSI Design
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
A
B
Y

CMOS VLSI Design
Compound Gates
 Compound gates can do any inverting function
 Ex:
A
B
C
D
A
B
C
D
A B C D
A B
C D
B
D
Y
A
C
A
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
Y = (A.B + C.D)’

CMOS VLSI Design
Example: O3AI
 Y = ((A+B+C).D)’

CMOS VLSI Design
Example: O3AI
 Y = ((A+B+C).D)’
A B
Y
C
D
D
C
B
A

CMOS VLSI Design
Signal Strength
 Strength of signal
– How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
– But degraded or weak 1
 pMOS pass strong 1
– But degraded or weak 0
 Thus nMOS are best for pull-down network

CMOS VLSI Design
Pass Transistors
 Transistors can be used as switches
g
s d
g
s d

CMOS VLSI Design
Pass Transistors
 Transistors can be used as switches
g
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0

CMOS VLSI Design
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well

CMOS VLSI Design
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0

CMOS VLSI Design
Tristates
 Tristate buffer produces Z when not enabled
EN A Y
0 0
0 1
1 0
1 1
A Y
EN
A Y
EN
EN

CMOS VLSI Design
Tristates
 Tristate buffer produces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A Y
EN
A Y
EN
EN

CMOS VLSI Design
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y
A Y
EN
EN

CMOS VLSI Design
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
Y
EN
EN

CMOS VLSI Design
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN

CMOS VLSI Design
Multiplexers
 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0
0 X 1
1 0 X
1 1 X
0
1
S
D0
D1
Y

CMOS VLSI Design
Multiplexers
 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1
Y

CMOS VLSI Design
Gate-Level Mux Design

 How many transistors are needed?
1 0 (too many transistors)
Y SD SD
 

CMOS VLSI Design
Gate-Level Mux Design

 How many transistors are needed? 20
1 0 (too many transistors)
Y SD SD
 
4
4
D1
D0
S Y
4
2
2
2 Y
2
D1
D0
S

CMOS VLSI Design
Transmission Gate Mux
 Nonrestoring mux uses two transmission gates

CMOS VLSI Design
Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
– Only 4 transistors
S
S
D0
D1
Y
S

CMOS VLSI Design
Inverting Mux
 Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
 Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S

CMOS VLSI Design
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects

CMOS VLSI Design
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates
S0
D0
D1
0
1
0
1
0
1
Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0

CMOS VLSI Design
D Latch
 When CLK = 1, latch is transparent
– D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
– Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latch
D
CLK
Q

CMOS VLSI Design
D Latch Design
 Multiplexer chooses D or old Q
1
0
D
CLK
Q
CLK
CLK
CLK
CLK
D
Q Q
Q

CMOS VLSI Design
D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q

CMOS VLSI Design
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
Flop
CLK
D Q
D
CLK
Q

CMOS VLSI Design
D Flip-flop Design
 Built from master and slave D latches
QM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latch
Latch
D Q
QM
CLK
CLK

CMOS VLSI Design
D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QM
Q
D
CLK
Q

CMOS VLSI Design
Race Condition
 Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
D
Q1
Flop
Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2

CMOS VLSI Design
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
– Industry manages skew more carefully instead
1
1
1
1
2
2
2
2
2
1
QM
Q
D

CMOS VLSI Design
Gate Layout
 Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

CMOS VLSI Design
Example: Inverter

CMOS VLSI Design
Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32  by 40 

CMOS VLSI Design
Stick Diagrams
 Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers

CMOS VLSI Design
Wiring Tracks
 A wiring track is the space required for a wire
– 4  width, 4  spacing from neighbor = 8  pitch
 Transistors also consume one wiring track

CMOS VLSI Design
Well spacing
 Wells must surround transistors by 6 
– Implies 12  between opposite transistor flavors
– Leaves room for one wire track

CMOS VLSI Design
Area Estimation
 Estimate area by counting wiring tracks
– Multiply by 8 to express in 

CMOS VLSI Design
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
– Y = ((A+B+C).D)’

CMOS VLSI Design
Example: O3AI
– Y = ((A+B+C).D)’

lecture 1 layout presentation of very large scale integration in digital electronics

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