This document describes a design for an approximate logarithmic multiplier that uses Mitchell's algorithm and operand decomposition to improve accuracy while maintaining low power consumption. It is intended for applications like convolutional neural networks and digital signal/image processing that require multiplication but not highly accurate results. The design takes two binary inputs, divides them into four parts using logic operations, and applies Mitchell's algorithm to each part separately before adding the results. This operand decomposition approach increases the accuracy over using Mitchell's alone. The design is implemented using Xilinx tools and simulation waveforms and block diagrams are provided to illustrate its operation. Experimental results show this approach reduces error compared to using just Mitchell's algorithm for multiplication.