Implementation of Fast Pipelined AES Algorithm on Xilinx FPGA

International Journal of Science and Research (IJSR), India Online ISSN: 2319-7064
Volume 2 Issue 8, August 2013
www.ijsr.net
Implementation of Fast Pipelined AES Algorithm
on Xilinx FPGA
Chityala Prathyusha1
, P. Sharmila Rani2
1
M. Tech Scholar, VLSI-SD, E.C.E Department, Teegala Krishna Reddy Engineering College, Hyderabad, India
2
Head, E.C.E Department, Teegala Krishna Reddy Engineering College, Hyderabad, India
Abstract: The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The
algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data.
Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations
can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to
malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind
attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and
reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick
alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher
throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption
and the key expansion module.
Keywords: Cryptography, AES, DES, FPGA, efficient encryption/decryption implementation, pipeline.
1. Introduction
In 1997, the National Institute of Standards and Technology
– NIST released a contest to choose a new symmetric
cryptograph algorithm that would be called Advanced
Encryption Standard – AES to be used to protect confidential
data in the USA. The algorithm should meet few
requirements such as copyright free, faster than the 3DES,
cryptograph of 128 bit blocks using 128, 192 and 256 bit
keys, possibility of hardware and software implementation,
among others. In 2000, after analysis by cryptography
experts, it was chosen the winner: Rijndael. The algorithm
was created by the Belgians Vincent Rijmen e Joan Daemen.
Hardware-based cryptography is used for authentication of
users and of software updates and installations. Software
implementations can generally not be used for this, as the
cryptographic keys are stored in the PC memory during
execution, and are vulnerable to malicious codes. Hardware-
based cryptography, when implemented in a secure manner,
is demonstrably being superior to software-based encryption.
Hardware-based encryption products can also vary in the
level of protection they provide against brute force rewind
attacks, offline parallel attacks, or other cryptanalysis attacks.
In this work we present an efficient cryptography hardware
implementation and its improvement using pipelines. The
algorithm was implemented in FPGA due to its flexibility and
reconfiguration capability. A reconfigurable device is very
convenient for a cryptography algorithm since it allows cheap
and quick alterations. Therefore, a new architecture was
developed using pipelines. The implementation of pipelined
cryptography hardware was used to improve performance in
order to achieve higher throughput and greater parallelism.
2. AES Rijndael
In order to better understand the AES structure it is necessary
to know the definition of state in the algorithm. State is the
matrix of bytes that is processed between many stages, or
rounds, and therefore, it will be modified in each stage. In the
Rijndael algorithm, the matrix size depends on the block size
being used, composed of 4 lines and Nb columns. Here, Nb
is the number of bits in the block, divided by 32, since 4
bytes represent 32 bits. Since the AES algorithm uses 128 bit
blocks, the state will be composed by 4 lines and 4 columns.
The key is grouped by the same fashion as the data block,
whereas Nk is the number of columns. Nr is the number of
rounds that will be run during the algorithm. The number of
runs in the
AES will depend on size of the key, where Nr will be 10, 12
and 14, for Nk equals to 4, 6 and 8, respectively. On the
encryption algorithm, there will be 4 phases: AddRoundKey,
SubBytes, ShiftRows and MixColumns. Nevertheless, on the
last stage, the MixColumns operation is suppressed. The
decryption algorithm will use the respective inverse
operations: InvAddRoundKey, InvSubBytes,
InvMixColumns and InvShiftRows. As it was in the
encryption phase, the InvMixColumns is suppressed on the
last stage of decryption algorithm. The algorithm will be
explained based on its specification. The values shown in the
example are presented in hexadecimal format.
A. SubBytes
Each state byte is replaced by another in the S-box
(replacement Box), as indicated in Fig. 1. The replacement
follows a matrix, where the first hexadecimal value
corresponds to the line positioning, and the second
hexadecimal value corresponds to the column positioning.
The inverse operation (decryption) is called InvSubBytes,
and uses an inverse S-Box. As an example, the S-box outputs
24 for the input value A6 (Figure 2 - line A, column 6). On
the same way, the inverse SBox outputs A6 for the input
value 24 (Figure 3 - line2, column4).
377

www.ijsr.net
.
Figure 1: SubBytes operation process
Figure 2: S-Box
Figure 3: InvS-Box
B. ShiftRows:
It consists of a left shift on the state lines, replacing therefore
their byte position, as indicated in Fig. 4. Line 0 suffers 0
shifting. Line 1 is shifted by one position and line 2
undergoes do 2 shifting positions. Line 3 is shifted by3
positions.
Figure 4: ShiftRows operation process.
The decryption algorithm performs the inverse operation
InvShiftRows that consists of similar shifting as the
ShiftRows, but shifted to the right.
C. MixColumns
In this operation, the state bytes are treated as polynomials of
Galois Field algebra GF (28). The operation can be
represented as a matrix multiplication, as indicated in Fig. 5,
where S is the initial state and S´ is the final state, after the
operation.
Figure 5: MixColumns operation process
The inverse operation, the InvMixColumns, consists of the
multiplication using the inverse matrix. In the last round, on
both the encryption and decryption algorithms, the
MixColumns operation is suppressed. The C matrix (used in
the encryption) and C´ matrix (used in the decryption) are
D. AddRoundKey
It is an XOR operation between the state and the round key
that it is generated from the main key through the Key
Generation. The matrix of keys is represented by w columns
or kx,y cells. AddRoundKey is used both in the encryption
and decryption algorithms. The XOR is conducted on byte
basis, as indicated in Fig 6, where the new byte
is given by
378

www.ijsr.net
Figure 6: AddRoundKey operation process
E. Key Expansion
The Key size defines the number of rounds in the
encryption/decryption algorithm, and it also defines its
expansion process. Basically, the Key Expansion operation
consists of three operations, as presented in Fig. 7. The first
operation, RotWord, makes a one byte circular shifting on
the word. The second operation, SubWord replaces each byte
of the input word according to the S-Box. The third operation
consists of XOR operations, as indicated in Figure 7.
Figure 7: KeyExpansion operation process
3. Initial Implementation
The AES hardware was implemented in three modules: the
encryption, the decryption and the key expansion module.
The hardware is implemented as illustrated in Fig.8. It is
composed of two 128 bit inputs that receive the key and the
initial word to be encrypted (signals IN_INI_KEY and
IN_INI_DATA).All the modules were independently tested
and characterized, and therefore they can be used in any
combination, according to the application. In order to
conduct tests on all blocks, it was assembled a 128 bits
encryption - decryption AES set in a Xilinx Spartan-3 FPGA.
After the tests on the Xilinx Spartan-3 FPGA, the hardware
was also tested on a Xilinx Virtex-5 FPGA. The VHDL
description implemented on both FPGAs is exactly the same,
and no change was made in the VHDL description to fit any
of the FPGAs. Important information is that the code is
totally portable, it can be used in any FPGA since it was
developed using the standard VHDL. Each module was
developed independently from the others, and them they were
mounted together.Figure8 shows the Encryption/Decryption
block with it’s I/Os. The round keys in which each key is
called; and the word of each phase of encryption that is used
after the calculations (feedback). The process consists of 10
rounds for 128 bits data .Each round consists of Substitute
bytes, Shift rows, Mix columns, Add round key blocks. After
10 rounds the obtained is the encrypted result. The encrypted
value is decrypted in another 10 rounds which are reverse to
encryption. The decryption cycle consists of 10 rounds .Each
round consists of Inverse Shift Rows, Inverse Sub bytes, Add
round key, Inverse mix columns.
Figure 8: Block Diagram of AES Algorithm
4. Pipelined Implementation
Pipelining is one of the most efficient means of improving
performance in high-end processor architectures. In order to
achieve higher throughput and greater instruction-level
Parallelism modern microprocessors contain deeply pipelined
function units with arbitrary structural hazards. Historically,
design techniques for hardware pipelines with structural
hazards have been successfully developed and used in vector
and pipelined supercomputers. The classical hardware
pipeline design theory developed more than 3 decades ago
was driven by this need. In our case, we used some levels of
cryptography pipelining and greater frequencies were
achieved. These levels of pipeline were implemented using
Xilinx Virtex-5.Using our modular blocks (Key Expansion,
Encrypt and Decrypt) we developed a pipelined cryptography
hardware with one, two and five levels of cryptography,
improving the efficiency of the process.
4.1 Pipelined Results Comparison
379

www.ijsr.net
The interval I/O represents the period of time that the data
buses will be idle. This interval was decreased from 13,5ns
(without pipelines) to 6 ns (with 5 levels of cryptography). It
does show a great improvement in hardware efficiency by
using the same FPGA board.
5. Chip Scope
Chip Scope is embedded, software based logic analyzer. By
inserting an “integrated controller core” (icon) and an
“integrated logic analyzer” (ila) into your design and
connecting them properly, you can monitor any or all of the
signals in your design. ChipScope provides you with a
convenient software based interface for controlling the
“integrated logic analyzer,” including setting the triggering
options and viewing the waveforms.
Figure 9: Chip Scope
Figure 10: Simulation Waveform
5.1 Waveform Description
RST is used to reset module or clear previous data, CLK is
used for the synchronization, when the raising edge of CLK
is ‘1’ then count is a counter, go on counting from ‘0’ to
‘10’.The decrypted value obtained at the decryption cycle is
same as the encrypted value at encryption cycle after 10
rounds for 128 bit key.
6. Conclusion
This paper presents an approach for the implementation of an
AES algorithm on an FPGA using VHDL high-speed and
high-density FPGAs. FPGAs features speed, accuracy,
power, compactness, and cost .Configurable latency,
resolution and pipelining. This article presented a fast and
efficient AES cryptography hardware structure that can find
many applications. The circuit implementation is very
efficient and can be customized to a wide range of
applications. The pipelining can be used in faster devices and
buses. It represents an improvement over the non-pipeline
version and can support many new applications.
References
[1] FIPS FIPS-197, Federal Information Processing
Standards Publication FIPS-197, Advanced Encryption
Standard (AES),
[2] http://csrc.nist.gov/publications/fips/fips197/fips-
197.pdf, 1999.
[3] Daemen, J. and Rijmen, V., The design of Rijndael: AES
— The Advanced Encryption Standard. Springer-Verlag,
2002
[4] Schneier, B., Applied Cryptography: Protocols,
Algorithms and Source Code in C. John Wiley & Sons,
Inc. 2nd Ed, 1996.
[5] Gomes, O. S. M.; Pimenta, T. C.; Moreno, R. L., "A
Highly Efficient FPGA Implementation", 2nd Latin
America Symposium on Circuits and Systems(LASCAS-
2011), February 2011.
[6] Daemen, J. and Rijmen, V. A Specification for the AES
Algorithm. NIST (National Institute of Standards and
Technology)
[7] http://csrc.nist.gov/archive/aes/rijndael/wsdindex.html,
2010.
[8] Klima, R. E., SIGMON, N., AND STITZINGER, E.
Applications of abstract algebra with Maple, CRC Press,
Boca Raton, FL. 2000.
[9] C. Chien, D. Chien, C. Chien, I. Verbauwhede and F.
Chang, "A hardware implementation in FPGA of the
Rijndael algorithm", The 2002 45th Midwest Symp.
Circuits and System (MWSCAS-2002), Vol. 1, 4 --.7
August 2002, pp. 507-509.
[10]I. Algredo-Badillo, C. Feregrino-Uribe and R. Cumlido-
Parra, "Design and implementation of an FPGA-based
1.452 Gbps nonpipelined AES architecture', The 2006
Int. Con! Computational Science and Its Applications
(ICCSA 2006), Lecture Notes in Computer Science, Vol.
3982 (Springer-Verlag, 2006), pp. 446--455
[11]J. Zambreno, D. Nguyen and A. Choudhary, "Exploring
area/delay
[12]tradeoffs in an AES FPGA implementation", Proc. Int.
Colif, Field Programmable Logic and Its Applications
(FPL), Lecture Notes in Computer Science, Vol. 3203
(Springer-Verlag 2004), pp. 575-585.
[13]E. J. Swankoski, V. Narayanan, M. Kandemir and M. J.
Irwin, "A parallel architecture for secure FPGA
symmetric encryption", 18th Int. Parallel and Distributed
Processing Symp. (IPDPS'04) - Workshop, Santa Fe,
New Mexico, 26-.30 April 2004, p. 123.
[14]E. Lopez-Trejo, F. Rodriguez-Henriquez and A. Diaz-
Perez, "An efficient FPGA implementation of CCM
using AES", The 8th Int. Con! Information Security and
Cryptology (ICJSC'05). Lecture Notes in Computer
Science (Springer 2005), pp. 208-215.
[15]Arshad Aziz and Nassar Ikram, "Memory efficient
implementation of AES S-boxes on FPGA", Journal of
Circuits, Systems, and Computers, Vol. 16, No.4 (2007)
603--611
380

www.ijsr.net
[16]Dur-e-Shahwar Kundi, Saleha Zaka, Qurat-Ul-Ain and
Arshad Aziz, "A Compact AES Encryption Core on
Xilinx FPGA", 2nd IEEE International Conference on
Computer, Control & Communication (IEEE IC4-2009)
Karachi, Pakistan Vol:1 pp:1-4, 2009.
[17]P. M. Kogge. “The Architecture of Pipelined
Computers”, McGraw-Hill Book Company, New York,
NY, 1981
[18]J.H. Pate1 and E.S. Davidson, “Improving the
throughput of a pipeline by insertion of delays”, In Proc.
of the 3rd Ann. Symp. On Computer Architecture, pages
159-164, Clearwater, FL, Jan. 19-21, 1976.
[19]N. Sklavos, X. Zhang, “Wireless Security &
Cryptography: Specifications and Implementations”,
CRC-Press, A Taylor and Francis Group. ISBN:
084938771X, 2007
381

Implementation of Fast Pipelined AES Algorithm on Xilinx FPGA

Recommended

More Related Content

What's hot (20)

Viewers also liked (9)

Similar to Implementation of Fast Pipelined AES Algorithm on Xilinx FPGA (20)

More from International Journal of Science and Research (IJSR) (20)

Recently uploaded (20)

Implementation of Fast Pipelined AES Algorithm on Xilinx FPGA