Iaetsd a novel vlsi dht algorithm for a highly modular and parallel

Abstract: A new very large scale integration (VLSI)
algorithm for a 2N-length discrete Hartley transform (DHT)
that can be efficiently implemented on a highly modular and
parallel VLSI architecture having a regular structure is
presented. The DHT algorithm can be efficiently split on
several parallel parts that can be executed concurrently.
Moreover, the proposed algorithms’ well suited for the sub
expression sharing technique that can be used to
significantly reduce the hardware complexity of the highly
parallel VLSI implementation. Using the advantages of the
proposed algorithm and the fact that we can efficiently share
the multipliers with the same constant, the number of the
multipliers has been significantly reduced such that the
number of multipliers is very small comparing with that of
the existing algorithms. Moreover, the multipliers with a
constant can be efficiently implemented in VLSI. Image
compression is largely possible by exploiting various kinds
of redundancies which are typically present in an image.
The extent of redundancies may vary from image to image.
Image compression algorithms aim to remove redundancy in
data in a way which makes image reconstruction possible.
This basically means that image compression algorithms try
to exploit redundancies in the data, they calculate which
data needs to be kept in order to reconstruct the original
image and therefore which data can be ‘thrown away. Image
compression and coding techniques explore three types of
redundancies: coding redundancy, inter pixel (spatial)
redundancy, and psycho visual redundancy. Coding
redundancy consists in using variable-length code words
selected as to match the statistics of the image itself or a
processed version of its pixel values. This type of coding is
always reversible and usually implemented using look-up
tables (LUTs).
Index Terms: Discrete Hartley transform (DHT), DHT
domain processing, fast algorithms
I. INTRODUCTION
The Discrete Fourier transform (DFT) is used in many
digital signal processing applications as in signal and image
compression techniques, filter banks, signal representation,
or harmonic analysis. The discrete Hartley transform (DHT)
can be used to efficiently replace the DFT when the input
sequence is real.
In the literature, there are some fast algorithms for the
computation of DHT and some algorithms for the
computation of generalized DHT.
There are also several split-radix algorithms for
computing DHT with a low arithmetic cost. Thus, Sorensen
et al. and proposed split-radix algorithms for DHT with a
low arithmetic cost proposed another split-radix algorithm
where the odd-indexed transform outputs are computed
using an indirect method.
The classical split-radix algorithm is difficult to
implement on VLSI due to its irregular computational
structure and due to the fact that the butterflies significantly
differ from stage to stage. Thus, it is necessary to derive
new such algorithms that are suited for a parallel VLSI
system.
There are also in the literature several fast algorithms
that use a recursive strategy as that for discrete cosine
transform (DCT) and that in for generalized DHT. Since
DHT is computationally intensive, it is necessary to derive
dedicated hardware implementations using the VLSI
technology.
One category of VLSI implementations is represented
by systolic arrays. There are many systolic array
implementations of DHT. Systolic array architectures are
modular and regular, but they use particularly pipelining and
not parallel processing to obtain a high-speed processing.
In the literature, highly parallel solutions as those in
and were also proposed. In, a highly parallel and modular
solution for the implementation of type-III DHT based on a
new VLSI algorithm is proposed. In, we have a highly
parallel solution for the implementation of DHT based on a
direct implementation of fast Hartley transform (FHT). It is
worth to note that hardware implementations of FHT are
rare.
Multipliers in a VLSI structure consume a large portion
of the chip area and introduce significant delays. This is the
reason why memory-based solutions to implement
multipliers have been more and more used in the literature.
To efficiently implement multipliers with lookup-table-
based solutions, it is necessary that one operand to be a
constant. When one of the operands is constant, it is
possible to store all the partial results in a ROM, and the
number of memory words is significantly reduced from 22L
to 2L
.
In this brief, a new VLSI DHT algorithm that is well
suited for a VLSI implementation on a highly parallel and
modular architecture is proposed. It can be used for
A NOVEL VLSI DHT ALGORITHM FOR A HIGHLY MODULAR AND PARALLEL
ARCHITECTURE
Pallala Pranaykumar1
, PG Student, Department of ECE, ASCET, Gudur, Andhra Pradesh, India.
Email: pranay441@gmail.com
D.Sreelakshmi2
, Associate professor, Department of ECE, ASCET, Gudur, Andhra Pradesh, India.
Email: doma.sreelakshmi@audisankara.com
Proceedings of International Conference on Advances in Engineering and Technology
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ISBN : 978 - 1505606395
International Association of Engineering and Technology for Skill Development
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designing a completely novel VLSI architecture for DHT.
Moreover, using sub expression sharing technique and
sharing the multipliers with the same constant, the hardware
complexity can be significantly reduced the number of
multipliers being very small, significantly less than that in.
In the proposed solution, we have used only multipliers with
a constant that can be efficiently implemented in VLSI. The
proposed solution is not only appealing by its high level of
parallelism and by using a modular and regular structure but
it can be also used to obtain a small hardware complexity by
extensively sharing the common blocks.
The rest of this brief is organized as follows. In Section
II, we present a DHT Transform. In Section III, we present a
Look-Up-Table. In Section IV, Simulation Results and The
conclusion and future works are presented in Section V.
II. DHT TRANSFORM
The Hartley transform is an integral transform closely
associated with the Fast Fourier Transform; however that
transforms real-valued functions to real-valued functions. it
absolutely was planned as an alternate to the Fourier
transform by R. V. L. Hartley in 1942, and is one in all
several noted Fourier-related transforms. Compared to the
Fourier transform, the Hartley transform has the benefits of
reworking real functions to real functions and of being its
own inverse. An FFT could be a thanks to work out
identical result more quickly: computing the DFT of N
points within the naive manner, victimization the definition,
takes O(N2) arithmetic operations, whereas a FFT will work
out an equivalent DFT in exactly O(N log N) operations.
The distinction in speed is huge, particularly for long
knowledge sets wherever N could also be within the
thousands or millions.
FFTs ar of nice importance to a decent type of
applications, from digital signal method and finding partial
differential equations to algorithms for fast multiplication of
enormous integers within the presence of round-off error,
several FFT algorithms are rather more correct than
evaluating the DFT definition directly.
2.1 Forward and Inverse Transform
The forward and inverse discrete Hartley transform pair
is given by
X (k) = ∑ X(n)cas (1)
X(n) = ∑ X (k) cas (2)
Where cas Φ = cos Φ + sin Φ.
H(u, v) f(x, y) ∙ {cos(2π) − + sin(2π)( − )
(3)
Where f(x, y) is the intensity of the pixel at position(x, y)
H(u,v)is the value of element in frequency domain. The
results are periodic and the cosine+sine (CAS) term is call
“the kernel of the transformation” (“or” basis function”).
The FHT are also used for fast arithmetic operation. In
Fast Hartley Transform (FHT) M and N must be power of 2.
Which are much faster than DHT? These equation form
representation is
H(u, v) = {T(u, v) + T(M − u, v) + T(u, N − v) −
T(M − u, N − v)}/2 (4)
For both the FFT and the FHT the complexity is
Nlog2N. An advantage of the DHT is the fact that the DHT
is self-inverse, so that only one software routine or hardware
device is needed for the forward and inverse FHT. For the
forward and inverse FFT of a real signal, two different
routines or devices are required.
The DHT is somehow conceptually easier than the DFT
if the signaling is real, however all operations is applied
with the FFT and also the FHT with an equivalent
complexness.
2.2 Relationship to Fourier Transforms
This transform differs from the classic Fourier
transform F (ω) =Ƒ {f (t)} (ω) in the choice of the kernel. In
the Fourier transform, we have the exponential kernel: exp
−iωt =cos ωt –isin (ωt) where i is the imaginary unit. The
two transforms are closely related, however, and the Fourier
transform (assuming it uses the same
√
normalization
convention) can be computed from the Hartley transform
via:
F(ω) =
( ) ( )
− i
( ) ( )
(5)
That is, the important and imagined elements of the
Fourier transform are merely given by the even and odd
elements of the Hartley transform, severally. Conversely,
for real-valued functions f (t), the Hartley transform is given
from the Fourier transform's real and imagined parts:
{Hf} = R{Ƒf} − I{Ƒf} = R{Ƒf ∙ (1 + i)} (6)
Where R and that I denote the important and imagined
elements of the complicated Fourier transform.
III. LOOK-UP-TABLE
To efficiently implement multipliers with lookup-table-
based solutions, it's necessary that one quantity to be a
continuing. once one in all the operands is constant, it's
potential to store all the partial leads to a read-only memory,
and therefore the variety of memory words is considerably
reduced from 22L
to 2L
. LUT in the main depends on RAM
blocks. we tend to might understand any logic operate from
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truth table victimization RAM, this can be done by mapping
the inputs to the address bus and therefore the output is
mapped to the information bus.
Fig.1. Block diagram of LUT
These Look-Up-Tables are very helpful to implement
the multiplier factor in Field Programmable Gate Array
(FPGA). The FPGA is one among the components in VLSI.
3.1 Parallel Process
Parallel version in the main used when combining a
bigger FFT with a three or five purpose FFT, since it's
possible to use three or five massive FFTs during a single
device.
3.2 Proposed System
Highly parallel and standard resolution for the
implementation of type-III DHT supported a replacement
VLSI rule is given. An extremely parallel resolution for the
implementation of DHT supported a direct implementation
of fast Hartley transforms (FHT). It’s value to notice that
hardware implementations of FHT are rare.
A new very large scale integration (VLSI) algorithmic
rule for a 2N
-length discrete Hartley transform (DHT) which
will be expeditiously enforced on an extremely standard and
parallel VLSI design having an everyday structure is
conferred. The DHT algorithmic rule will be expeditiously
split on many parallel elements which will be dead at the
same time. Moreover, the projected algorithmic rule is
compatible for the sub expression sharing technique which
will be wont to considerably reduce the hardware quality of
the extremely parallel VLSI implementation. Using the
benefits of the projected algorithmic rule and also the fact
that we will efficiently share the multipliers with constant,
the quantity of the multipliers has been considerably
reduced specified the quantity of multipliers is incredibly
tiny examination with that of the existing algorithms.
Moreover, the multipliers with a relentless will be
expeditiously enforced in VLSI.
IV. RESULTS
4.1 Simulation Results
Stage box 1
The above simulation shows the twiddle factor
distributed for the multipliers W0..W3 represents the
twiddle factors in memory .f0 ....f3 represents the switching
activity of multiplier
Stage box 2
The above simulation shows the twiddle factor
distributed for the multipliers W0..W3 represents the
twiddle factors in memory .f0 ....f3 represents the switching
activity of multiplier. The multiplier consists of 1 and -1.
Stage 3
the above simulation shows the twiddle factor distributed
for the multipliers W0..W3 represents the twiddle factors in
memory .f0 ....f3 represents the switching activity of
multiplier. As the multiplier consists of common digits -1
and 1 .it can be re-shared.
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Top module
The above simulation is the real values obtained and the
imaginary vales are set to zero two successive inputs are
given the sel line represents the inverse and normal DHT
output.
Multiplication
the above simulation is the multiplier output for the twiddle
factors and the inputs .the outputs are shown by out1 to
out4.
the above simulation is the multiplier output for the twiddle
factors and the inputs .the outputs are shown by out1 to
out4.
Imaginary multiplication
The above simulation is the multiplier output for the
twiddle factors and the inputs .the imaginary multiplication
is done by using the polarity in inverse.
4.2 Synthesis Report
RTL schematic
RTL VIEW
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Design Summery
V. CONCLUSION AND FUTURE SCOPE
A DHT transform of 8 bit input is being implemented
with radix 4 implementation. The selection line is the switch
for DHT and its inverse .a variable length of inputs have
been tested and synthesized. FFT has consumed 8 adders 4
multipliers where as the proposed scheme has only 4 adders
and 2 sharing multipliers as one of the twiddle factor is one.
Implementation is done in verilog language using Xilinx
tool.
Future Scope
Split-radix techniques are very attractive since they
provide both compact size and minimum operation counts.
As processors evolve, the finite register set limitation also
becomes less stringent. Such an environment could be
used to exploit the advantages of the larger and more
complex algorithms like vector radix techniques. Many
promising hybrid techniques have been also developed
and deserve attention.
Image should also support saving the FHT Buffer to
disk as well as its power spectrum. The ability to view and
alter the amplitude and phase of images should also be
supported. Finally, the dyadic frequency domain operations
deserve optimization, since their speed could double with-
out too much difficulty.
VI. REFERENCES
[1] Doru Florin Chiper, Senior Member, IEEE, “A Novel
VLSI DHT Algorithm for a Highly Modular and Parallel
Architecture”, IEEE Transactions on Circuits and
Systems—Ii: Express Briefs, Vol. 60, No. 5, May 2013.
[2]. R.E. Crochiere and L.R.Rabiner, Multi-rate Digital
Signal Processing. Englewood Cliffs, NJ, USA: Prentice-
Hall, 1983.
[3]. Z. Wang, “Harmonic analysis with a real frequency
function, I Aperiodic case, II Periodic and bounded cases,
and III data sequence,” Appl. Math. Comput vol. 9, no. 1,
pp. 53–73, Jul. 1981.
[4]. G. Bi, Y. Chen, and Y. Zeng, “Fast algorithms for
generalized discrete Hartley transform of composite
sequence length,” IEEE Trans. Circuits Syst. II, Analog
Digit. Signal Process, vol. 47, no. 9, pp. 893–901, Sep.
2000.
[5]. D. F. Chiper, “Radix-2 fast algorithm for computing
discrete Hartley transform of type III,” IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 59, no. 5, pp. 297–301, May 2012.
[6]. H. Z. Shu, J. S. Wu, C. F. Yang, and L. Senhadji, “Fast
radix-3 algorithm for the generalized discrete Hartley
transform of type II,” IEEE Signal Process. Lett, vol. 19, no.
6, pp. 348–351, Jun. 2012.
[7]. G. Bi, “New split-radix algorithm for the discrete
Hartley transform,” IEEE Trans. Signal Process., vol. 45,
no. 2, pp. 297–302, Feb. 1997.
[8]. P. K. Meher, J. C. Patra, and M. N. S. Swamy, “High
throughput memory based architecture for DHT using a new
convolution formulation,” IEEE Trans. Circuits Syst. II,
Exp. Briefs, vol. 54, no. 7, pp. 606–610, Jul. 2007.
[9]. P. K. Meher, T. Srikanthan, and J. C. Patra, “Scalable
and modular memory-based systolic array architectures for
discrete Hartley transform,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 53, no. 5, pp. 1065–1077, May 2006.
[10]. P. K. Meher, “LUT optimization for memory-based
computation,” IEEE Trans. Circuits Syst. II, Exp. Briefs,
vol. 57, no. 4, pp. 285–289, Apr. 2010.
[11]. D. F. Chiper and P. Ungureanu, “Novel VLSI
algorithm and architecture with good quantization properties
for a high-throughput area efficient systolic array
implementation of DCT,” EURASIP J. Adv. Signal
Process., vol. 2011, no. 1, pp. 1–14, Jan. 2011.
[12] H. V. Sorensen, D. L. Jones, C. S. Burrus, and M. T.
Heideman, “On computing the discrete Hartley transform,”
IEEE Trans. Acoust., Speech, Signal Process., vol. ASSP-
33, no. 5, pp. 1231–1238, Oct. 1985.
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