Graph based transistor network generation method for supergate design

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This paper proposes a novel graph-based method to automatically generate optimized transistor networks from a sum-of-products expression to improve speed, power, and area of VLSI circuits. The method identifies efficient sub-networks ("kernels") from the graph representation and combines them, with transistor sharing, into a single minimized network. Experimental results show transistor count reduction compared to other approaches, leading to gains in gate performance, power, and area. The method was implemented in software simulation tools and on Spartan FPGA hardware.

Graph-Based Transistor Network Generation Method for
Supergate Design
ABSTRACT:
Transistor network optimization represents an effective way of improving VLSI
circuits. This paper proposes a novel method to automatically generate networks
with minimal transistor count, starting from an irredundant sum-of-products
expression as the input. The method is able to deliver both series–parallel (SP) and
non-SP switch arrangements, improving speed, power dissipation, and area of
CMOS gates. Experimental results demonstrate expected gains in comparison with
related approaches.
EXISTING SYSTEM:
IN VLSI digital design, the signal delay propagation, power dissipation, and area
of circuits are strongly related to the number of transistors (switches) [1]–[3].
Hence, transistor arrangement optimization is of special interest when designing
standard cell libraries and custom gates [4], [5]. Switchbased technologies, such as
CMOS, FinFET [6], and carbon nanotubes [7], can take advantage of such an

improvement. Therefore, efficient algorithms to automatically generate optimized
transistor networks are quite useful for designing digital integrated circuits (ICs).
Several methods have been presented in the literature for generating and
optimizing transistor networks. Most traditional solutions are based on factoring
Boolean expressions, in which only series–parallel (SP) associations of transistors
can be obtained from factored forms [8]–[11]. On the other hand, graph-based
methods are able to find SP and also non-SP (NSP) arrangements with potential
reduction in transistor count [12]–[15].
PROPOSED SYSTEM:
The proposed method starts from a sum-ofproducts (SOP) form F and produces a
reduced transistor network. It comprises two main modules: 1) kernel identification
and 2) network composition. The former aims to find efficient SP and NSP switch

networks through graph structures called kernels. The latter receives the partial
networks obtained from the first module and performs switch sharing, resulting in
a single network representing F. Results have shown a significant reduction in
transistor count when compared with other approaches [10]–[14]. Experiments
have also demonstrated an improvement in performance, power dissipation, and
area of CMOS gates as a consequence of such a device saving.
SOFTWARE IMPLEMENTATION:
 Modelsim 6.0
 Xilinx 14.2

HARDWARE IMPLEMENTATION:
 SPARTAN-III, SPARTAN-VI

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