Error Identification in RAM using Input Vector Monitoring Concurrent BIST Architecture

65 International Journal for Modern Trends in Science and Technology
Volume: 2 | Issue: 10 | October 2016 | ISSN: 2455-3778IJMTST
Error Identification in RAM using Input
Vector Monitoring Concurrent BIST
Architecture
A. Rakesh1
| T. Pradeep Kumar2
1PG Scholar, Vaagdevi College of Engineering, Telangana.
2Assistant Professor, Vaagdevi College of Engineering, Telangana.
Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal
operation of the Random Access Memory without imposing a need to set the RAM offline to perform the test.
These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the
time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel
input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called
window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like
structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the
proposed scheme is shown to perform significantly better than previously proposed schemes with respect to
the hardware overhead and CTL tradeoff..
KEYWORDS: Built-in self-test, design for testability, testing.
Copyright © 2016 International Journal for Modern Trends in Science and Technology
All rights reserved.
I. INTRODUCTION
Built-in self test (BIST) techniques constitute a
class of schemes that provide the capability of
performing at-speed testing with high fault
coverage, whereas simultaneously they relax the
reliance on expensive external testing equipment.
Hence, they constitute an attractive solution to the
problem of testing VLSI devices [1]. BIST
techniques are typically classified into offline and
online. Offline architectures operate in either
normal mode (during which the BIST circuitry is
idle) or test mode. During test mode, the inputs
generated by a test generator module are applied to
the inputs of the circuit under test (RAM) and the
responses are captured into a response verifier
(RV). Therefore, to perform the test, the normal
operation of the CUT is stalled and, consequently,
the performance of the system in which the circuit
is included, is degraded.
Input vector monitoring concurrent BIST
techniques [2]–[10] have been proposed to avoid
this performance degradation. These architectures
test the RAM concurrently with its normal
operation by exploiting input vectors appearing to
the inputs of the CUT; if the incoming vector
belongs to a set called active test set, the RV is
enabled to capture the RAM response. The block
diagram of an input vector monitoring concurrent
BIST architecture is shown in Fig. 1. The CUT has
n inputs and m outputs and is tested exhaustively;
hence, the test set size is N = 2n . The technique
can operate in either normal or test mode,
depending on the value of the signal labeled T/N.
During normal mode, the vector that drives the
inputs of the RAM (denoted by d[n:1] in Fig. 1) is
driven from the normal input vector ( A[n:1]). A is
also driven to a concurrent BIST unit (CBU), a hit
has occurred. In this case, A is removed from the
active test set and the signal response verifier
enable (rve) is issued, to enable the m-stage RV to
capture the CUT response to the input vector [1].
The concurrent test latency (CTL) of an input
vector monitoring scheme is the mean time
(counted either in number of clock cycles or time
units) required to complete the test while the CUT
operates in normal mode.
ABSTRACT

Error Identification in RAM using Input Vector Monitoring Concurrent BIST Architecture
Fig. 1. Input vector monitoring concurrent BIST.
In this brief, a novel input vector monitoring
concurrent BIST scheme is proposed, which
compares favorably to previously pro-posed
schemes [2]–[7] with respect to the hardware
overhead/CTL tradeoff. This brief is organized as
follows. In Section II, we introduce the proposed
approach and in Section III, we calculate its
hardware overhead. In Section IV, we compare the
proposed scheme with previ-ously proposed input
vector monitoring concurrent BIST techniques. A
case study for the concurrent testing of ROM
modules is presented in Section V. Finally, Section
VI summarizes the conclusion of this brief.
II. PROPOSED SCHEME
Let us consider a combinational CUT with n
input lines, as shown in Fig. 2; hence the possible
input vectors for this CUT are 2n . The proposed
scheme is based on the idea of monitor-ing a
window of vectors, whose size is W , with W = 2w ,
where w is an integer number w < n. Every
moment, the test vectors belonging to the window
are monitored, and if a vector performs a hit, the
RV is enabled.
The bits of the input vector are separated into two
distinct sets comprising w and k bits, respectively,
such that w + k = n. The k (high order) bits of the
input vector show whether the input vector belongs
to the window under consideration. The w
remaining bits show the relative location of the
incoming vector in the current window. If the
incoming vector belongs to the current window and
has not been received during the examination of
the current window, we say that the vector has
performed a hit and the RV is clocked to capture
the CUT’s response to the vector. When all vectors
that belong to the current window have reached the
CUT inputs, we proceed to examine the next
window.
The module implementing the idea is shown in
Fig. 2. It operates in one out of two modes, normal,
and test, depending on the value of the signal T /N.
When T /N = 0 (normal mode) the inputs to the
CUT are driven by the normal input vector. The
inputs of the CUT are also driven to the CBU as
follows: the k (high order) bits are driven to the
inputs of a k-stage comparator; the other inputs of
the comparator are driven by the outputs of a
k-stage test generator TG.
The proposed scheme uses a modified decoder
(denoted as m_dec in Fig. 2) and a logic module
based on a static-RAM (SRAM)-like cell, as will be
explained shortly.
Fig. 2. Proposed architecture.
Fig. 3. Modified decoder design used in the
proposed architecture.
Fig. 4. Proposed architecture for n = 5, w = 3, and k = 2.

Fig. 5. Design of the logic module.
tge is disabled and cmp is enabled, the module
operates as a normal decoding structure. The
architecture of the proposed scheme for the specific
case n = 5, k = 2, and w = 3, is shown in Fig. 4. The
module labelled logic in Fig. 4 is shown in Fig. 5. It
comprises W cells (operating in a fashion similar to
the SRAM cell), a sense amplifier, two D flip-flops,
and a w-stage counter (where w = log2 W ). The
overflow signal of the counter drives the tge signal
through a unit flip-flop delay. The signals clk_ and
clock (clk) are enabled during the active low and
high of the clock, respectively. In the sequel, we
have assumed a clock that is active during the
second half of the period, as shown in Fig. 5.
In the sequel, we describe the operation of the
logic module, presenting the following cases: 1)
reset of the module; 2) hit of a vector (i.e., a vector
belongs in the active window and reaches the CUT
inputs for the first time); 3) a vector that belongs in
the current window reaches the CUT inputs but
not for the first time; and 4) tge operation (i.e., all
cells of the window are filled and we will proceed to
examine the next window).
A. Reset of the Module
At the beginning of the operation, the module is
reset through the external reset signal. When reset
is issued, the tge signal is enabled and all the
outputs of the decoder (Fig. 3) are enabled. Hence,
DA1, DA2, . . . , DAW are one; furthermore, the CD_
signal is enabled; therefore, a one is written to the
right hand side of the cells and a zero value to the
left hand side of the cells.
B. Hit of Vector (i.e., Vector Belongs in the Active
Window and Reaches the CUT Inputs for the First
Time)
The design of the m_dec module for w = 3 is
shown in Fig. 3 and operates as follows. When test
generator enable (tge) is enabled, all outputs of the
decoder are equal to one. When comparatot (cmp)
is disabled (and tge is not enabled) all outputs are
disabled. When during normal mode, the inputs to
the CUT are driven from the normal inputs. The n
inputs are also driven to the CBU as follows: the w
low-order inputs are driven to the inputs of the
decoder; the k high order inputs are driven to the
inputs of the comparator. When a vector belonging
to the current window reaches the inputs of the
CUT, the comparator is enabled and one of the
outputs of the decoder is enabled. During the first
half of the clock cycle (clk_ and cmp are enabled)
the addressed cell isread; because the read value is
zero, the w-stage counter is triggered through the
NOT gate with output the response verifier enable
(rve) signal. During the second half of the clock
cycle, the left flip-flop (the one whose clock input is
inverted) enables the AND gate (whose other input
is clk and cmp), and enables the buffers to write
the value one to the addressed cell.
Table I Calculation Of The Hardware Overhead Of The
Proposed Scheme
Table II Calculation Of The Hardware Overhead Of
Competing Schemes
Fig. 6. Input vector monitoring techniques:
comparison (n = 16, m = 16, and 100-MHz clock).

C. Vector That Belongs in the Current Window
Reaches the CUT Inputs But Not for the First Time
If the cell corresponding to the incoming vector
contains a one (i.e., the respective vector has
reached the CUT inputs during the examination of
the current window before), the rve signal is not
enabled during the first half of the clock cycle;
hence, the w-stage counter is not triggered and the
AND gate is not enabled during the second half of
the clock cycle.
D. tge Operation (i.e., All Cells of the Window are
Filled and We Will Proceed to Examine the Next
Window)
When all the cells are full (value equal to one),
then the value of the w-stage counter is all one.
Hence, the activation of the rve signal causes the
counter to overflow; hence in the next clock cycle
(through the unit flop delay) the tge signal is
enabled and all the cells (because all the outputs of
the decoder of Fig. 3 are enabled) are set to zero.
When switching from normal to test mode, the
wstage counter is reset. During test mode, the
w-bit output of the counter is applied to the CUT
inputs. The outputs of the counter are also used to
address a cell. If the cell was empty (reset), it will be
filled (set) and the RV will be enabled. Otherwise,
the cell remains full and the RV is not enabled.
III. CALCULATION OF HARDWARE OVERHEAD
The hardware overhead of the proposed scheme
is calculated using the gate equivalents as a metric.
One gate equivalent or gate is the hardware
equivalent of a two-input NAND gate. The
parameters that affect the hardware overhead of
the proposed scheme are n (the number of CUT
inputs), m (the number of CUT outputs), and w
(representing the window size) with k = n − w and W
= 2w .
Fig. 7. Hardware overhead versus CTL for the proposed
scheme (64 k × 16 ROM operating at 100 MHz).
Table III Comparison Of The Schemes For The
Concurrent Testing Of Various Rom Sizes
The implementation of the scheme requires the
nstage multiplexer at the inputs of the CUT, and an
mstage order-independent RV. The necessity to
have an order-independent response verification
scheme stems from the fact that, during the
examination of any window of vectors, the order
that the vectors will perform hit, is not fixed. The
accumulator-based compaction of the responses is
an order-independent response verification
technique [11], [12] that has been shown to have
aliasing properties similar to the best compactors
based on cellular automata and multiple input
signature registers. Furthermore, the
accumulator-based compaction requires only a
onebit full adder (FA) and a D-type flip-flop (DFF)
for each CUT output. Therefore, the
accumulator-based compaction of the responses is
used for the implementation of the proposed
scheme. In Table I, the hardware overhead of the
various modules of the proposed scheme has been
calculated, following Figs. 2–5. We have estimated
the overhead of one cell as 1.5 gate equivalents, the
overhead of a tristate buffer as one gate, and the
overhead of a sense amplifier as three gates.
IV. COMPARISONS
To evaluate the presented scheme, we compare it
with the input vector monitoring concurrent BIST
techniques proposed hitherto. Because for the
same window size W , the CTL is equal to the
scheme proposed in [3] and [7] for the same
window size, in the sequel, we proceed using the
CTL calculated in these publications. C-BIST [4]
was the first input vector monitoring concurrent
BIST technique proposed, and suffers from long
CTL; therefore modifications have been proposed,
Multiple Hardware Sig-nature Analysis Technique
(MHSAT) [5], Order Independent Signature
Analysis Technique (OISAT) [6], RAM-based

Concur-rent BIST (R-CBIST) [2], Window -
Monitoring Concurrent BIST (w-MCBIST) [3], and
Square Windows Monitoring Concurrent BIST
(SWIM) [7]. The comparisons will be performed with
respect to the value of the CTL and the hardware
overhead.
In Table II, we provide the formulas that we used to
calculate the hardware overhead of MHSAT, OISAT
(K = 2k ), R-CBIST, w-MCBIST, and the SWIM
scheme. The cells used are two-input XOR gate
(XOR2), n-input AND gate(ANDn ), n-input NAND
gate (NANDn ), n-input OR gate (Rn ), n-input NOR
gate (NORn ), DFF, FA and two-to-one multiplexer
(MUX21).
In Fig. 6, the CTL is presented (in time units, i.e.,
seconds) as a function of the hardware overhead (in
gate equivalents) for R-CBIST, w-MCBIST, SWIM,
and the proposed architecture. A CUT with n = 16
inputs and m = 16 outputs has been considered.
The points have been connected with power trend
lines. From Fig. 6, we can observe that for the same
hardware overhead, proposed scheme achieves
shorter CTL than the previously proposed
schemes. Thus, we conclude that the proposed
scheme is more efficient than MHSAT, OISAT,
w-MCBIST, and SWIM with respect to the hardware
overhead—CTL tradeoff. For example, if a CTL of 3
s is required, then the proposed scheme requires
761 gates, whereas SWIM (the second better
scheme) requires 898 gates, i.e., 16% more and
w-MCBIST requires 1136 gates, i.e., 33% more.
Furthermore, if the demand for CTL is not < 0.8
s, the proposed scheme achieves the same CTL
with R-CBIST with significantly less hardware
overhead. For example, for CTL = 3 s, the hardware
overhead required by the proposed scheme is 761
gates, whereas the same number for R-CBIST is
1553, i.e., 102% more.
V. CASE STUDY: COMPARATIVE CONCURRENT
TESTING OF ROM MODULES
ROM modules require high-quality testing
because they constitute critical parts in complex
circuits, therefore testing schemes for ROMs use
exhaustive application of input patterns, which
has been proved to cover all logically testable
combinational faults [14]. For the calculations, we
have considered a ROM cell to be equivalent to 1/4
gate (as in [13]). For the case considered in Fig. 6 (a
64 k × 16 word memory), the overhead of the ROM
is calculated by multiplying the number of cells (64
k × 16 = 65 536 × 16 = 1 048 576) with 1/4, giving
262 144 gates. Fig. 7 shows the percentage of
hardware overhead of the proposed scheme as a
function of the CTL assuming a 100-MHz clock.
From Fig. 7, we can observe that the concurrent
test can be completed within < 4 s with < 0.4%
overhead, as shown with the dashed line. It should
be noted that, because of problems with layout, the
actual area overhead may be higher; however, the
above calculations give an indicative order of
magnitude for the relative hardware overhead of
the proposed scheme.
In Table III, we compare the w-MCBIST, SWIM,
and the proposed scheme for the concurrent
testing of ROMs with representative sizes. We have
not considered R-CBIST in these comparisons,
because for these values of the CTL, the R-CBIST
scheme does not give favorable results, as shown in
Fig. 6. For the calculations, we have considered
ROMs with 16-bit words and a 100-MHz clock. In
Table III, for every ROM size, we present a group of
six rows. In the first row of each group, we present
the CTL (s); in the three following rows of each
group, we present the hardware overhead of each
scheme as a percentage of the hardware overhead
of the ROM module. In the last two rows of every
group, we present the decrease of the proposed
scheme over the w-MCBIST scheme (denoted
Decrease1) and over the SWIM scheme (denoted
Decrease2).
From Table III, the following conclusions can be
drawn.
1 The hardware overhead of the proposed
scheme is lower than the other schemes for all
the entries of the table.
2 The decrease in hardware overhead obtains
higher as the CTL decreases; for example, in
the 256-k ROM group, the decrease (compared
with SWIM) is 11.11% when a CTL = 50.94 s is
required, it climbs up to 38.46% when the
required CTL is ∼5 s.
VI. CONCLUSION
BIST schemes constitute an attractive solution to
the problem of testing VLSI devices. Input vector
monitoring concurrent BIST schemes perform
testing during the circuit normal operation without
imposing a need to set the circuit offline to perform
the test, therefore they can circumvent problems
appearing in offline BIST techniques. The
evaluation criteria for this class of schemes are the
hardware overhead and the CTL, i.e., the time
required for the test to complete, while the circuit
operates normally. In this brief, a novel input
vector monitoring concurrent BIST architecture

has been presented, based on the use of a
SRAM-cell like structure for storing the
information of whether an input vector has
appeared or not during normal operation. The
proposed scheme is shown to be more efficient
than previously proposed input vector monitoring
concurrent BIST techniques in terms of hardware
overhead and CTL.
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