SlideShare a Scribd company logo
Information Theory & Coding
Unit V :
Measure of Information, Source Encoding, Error Free Communication over a Noisy Channel capacity of a
discrete and Continuous Memoryless channel Error Correcting codes: Hamming sphere, Hamming
distance and Hamming bound, relation between minimum distance and error detecting and correcting
capability, Linear block codes, encoding & syndrome decoding; Cyclic codes, encoder and decoders for
systematic cycle codes; convolution codes, code tree & Trellis diagram, Viterbi and sequential decoding,
burst error correction, Turbo codes.
4/2/2018 1
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Error Correcting Coding
4/2/2018 2
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
In Digital Communication, two important parameters in design are SNR Eb/No and
bandwidth B and objective is to achieve acceptable reliability (error rate) of
transmission.
For a given Eb/No only coding (adding systematic redundancy) can ensure acceptable
error rate of transmission.
Error Control can be done by
• FEC: forward error correction (Error detection and correction)
• ARQ: Automatic request for retransmission (Error detection)
Error control coding is systematic addition redundancy for error detection and correction.
Hamming sphere, Hamming distance, Hamming weight,
Hamming bound, and error correcting capability
4/2/2018 3
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Let a pair of code vectors are x and y that have same number of elements
• Hamming distance d(x,y) between such pair of code vectors is defined as number of
locations in which their respective locations.
• Hamming weight w(x) of a code vector x is defined as the number of non zero
elements of the code vector
• Minimum distance dmin of linear code block is smallest hamming distance between
any pair of code vectors in the code.
• For the (n,k) linear block code, to be able to correct upto t bits of error (all error
patterns of t bits or less) if and only if d(xi, xj) ≤ 2t+1 for all xi and xj
• Hamming bound (n,k) block code can correct upto t errors provided Hamming bound
is satisfied. For equality code is said to be perfect
0
2
t
n k
i
n
i


 
  
 

Linear Block Codes
4/2/2018 4
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
(n,k) linear block has n code bits of which consists of k message bits and n-k parity bits.
b0, b1, ------------------, bn-k-1, m0, m1, ------------------, mk-1,
N-k Parity bits K Message bits
,0 ,1 1 , 1 1
0,1, , 1
code where are parity bits and are message bits
, 1, , 1
parity bits (all arithmatic in coding are modulo 2
i
i i i
i k n
i i o i i k k
b i n k
x b m
m i n k n k n
b p m p m p m
 
 
     
 
       
        
,
0 1 1 0 1 1
k
k
operations)
1 if depends on
where
0 otherwise
Let message [ , , ] and parity [ , , ]
code [ ] [ ] [ I ]
Let us define Generator Matrix =[ I ]
i j
i j
k k
b m
p
m m m m b b b b m p
x b m m p m m p
G p
 

 

        
  
Linear Block Codes
4/2/2018 5
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
n-k
n-k n-k n-k
n-k
then code vector
Let us define parity cheker Matrix =[I ]
then = I I I 0=
I
Again received vector = + where e is error vector added due to noise
Synd
T
T
T T T T T
x m G
H p
p
HG p p p GH
y x e

 
         
 rome = + [ 0]T T T T
s y H x e H eH GH  
• Syndrome depends on error pattern and not on codeword sent
• All error pattern that differs by a codeword have same syndrome
• A syndrome is sum of those columns of parity check matrix corresponding to error location
• (n,k) block code can correct upto t errors provided Hamming bound is satisfied.
• A code (n,k) is said to be perfect, if equality holds in Hamming bound
Cyclic codes
4/2/2018 6
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Cyclic codes are subclass of linear block codes and are easy to encode. A cyclic code exhibits
• Linearity property: Sum of two codewords is also a codeword.
• Cyclic property: Cyclic shift of any codeword is also a codeword.
If (x0, x1,--- xn-1) is codeword of (n,k) linear block code and is cyclic then
(xn-1, x0,--- xn-2)
(xn-2, xn-1,--- xn-3)
.
.
(x1, x2,----- x0) are all valid codewords
Cyclic codes
4/2/2018 7
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Codeword polynomial for code (x0, x1,-- ,xn-1) is codeword is written as
x(D)= x0+ x1D+x2D+--------+ xn-1Dn-1
where D is a real variable, s.t Dn =1
The condition Dn =1 ensures
• Codeword polynomial is of the order n-1 for a multiplication with D
• Multiplication by D to the polynomial makes circular right shift
• This leads to multiplication modulo Dn -1
D x(D) modulo (Dn-1) = xn-1+ x0D+x1D2+--------+ xn-2Dn-1
D2 x(D) modulo (Dn-1) = xn-2+ xn-1D+x0D2+--------+ xn-2Dn-1
Di x(D) modulo (Dn-1) is codeword polynomial for a cyclic shift i.
Cyclic codes
4/2/2018 8
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Generator Polynomial g(D)
g(D) is a factor of (Dn+1) having minimum degree n-k
X(D)= a(D) g(D) modulo (Dn-1) where a(D) is polynomial
Encoding Procedure:
• Multiply message polynomial m(D) by Dn-k
• Divide Dn-k m(D) by g(D) and obtain remainder b(D)
• Add b(D) Dn-k m(D) giving codeword
Parity Check polynomial h(D)
h(D) g(D) modulo (Dn-1)=0 [like HGT=0]
or h(D) g(D) =Dn+1
Cyclic codes
4/2/2018 9
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
(7,4) Hamming Code Ex. 1+Dn= (1+D)(1+D2+D3)(1+D+D3)
Let g(D)= 1+D+D3
then h(D)= (1+D)(1+D2+D3)= 1+D+D2+D3+D3+D4=1+D+D2+D4
G matrix can be constructed using
g(D)= 1+ D+0D2+ D3+0D4+0D5+0D6
Dg(D)= 0+ D+ D2+0D3+ D4+0D5+0D6
D2g(D)=0+0D+ D2+ D3+0D4+ D5+0D6
D3g(D)=0+0D+0D2+ D3+ D4+0D5+ D6
1 1 0 1 0 0 0
0 1 1 0 1 0 0
0 0 1 1 0 1 0
0 0 0 1 1 0 1
G
 
 
 
 
 
 
1 1 0 1 0 0 0
0 1 1 0 1 0 0
1 1 1 0 0 1 0
1 0 1 0 0 0 1
G
 
 
 
 
 
 
G can be made systematic by using
row operations make 4x4 identity
matrix in last columns
R3→R3+R1 and R4→R1+R2 +R4
Encoder for Cyclic codes:
Ex. (7,4) Hamming Code Encoder
4/2/2018 10
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Let g(D)= 1+D+D3
Then encoder can be easily made using Flip
Flops as shown in figure
It requires 3 FF, input/ output to each FF is
marked. mod 2 addition is done for terms.
For message 1001
Parity bits generated are 011
Code : 0111001
FFFFFF
Gate
D0=1 D D2 D3
message bits
Parity
bits
Encoded
bits
Shift input Register
output
0 0 0
1 1 1 1 0
2 0 0 1 1
3 0 1 1 1
4 1 0 1 1
Syndrome calculation for Cyclic codes:
Ex. (7,4) Hamming Code Syndrome
4/2/2018 11
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Let g(D)= 1+D+D3
Then parity checker (syndrome) can be made
using Flip Flops as shown in figure
It requires 3 FF, input/ output to each FF is
marked. mod 2 addition is done for terms.
For message 1001, Parity is 011
Transmitted Code: 0111001
If received vector : 0111001
Syndrome 000 No error
If received vector : 0110001
Syndrome 110 error vector 0001000
Shift input Register
output
0 0 0
1 1 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 1 0
5 1 1 0 1
6 1 0 0 0
7 0 0 0 0
FFFFFF
Gate
D0=1 D D2 D3
Syndrome for no error
Shift input Register
output
0 0 0
1 1 1 0 0
2 0 0 1 0
3 0 0 0 1
4 0 1 1 0
5 1 1 1 1
6 1 0 0 1
7 0 1 1 0
Syndrome for error vector
0001000
Important cyclic codes
4/2/2018 12
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
• Cyclic Redundancy check codes (CRC):
▪ (18,6) CRC-12 g(D)=1+D+D2+D3+D11+D12
▪ (24,8) CRC-16 g(D)=1+D2+D15+D16
▪ (24,8) CRC-CCITT g(D)=1+D5+D12+D16
• Golay codes: Three error correcting perfect cyclic code
▪ (23,12) g(D)=1+D+D5+D6+D7+D9+D11
• Bose- Chaudhuri Hocquenqhem (BCH):
▪ Each BCH code is t error correcting code
▪ (15,7) 2 error corrrection g(D)=1+D4+D6+D7+D8
convolution codes
4/2/2018 13
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
• Block codes are produced on block by block basis, thus
requires a buffer.
• For serial inputs, convolutional codes are preferred
• Convolution coding operates on serial incoming bits
• A binary convolutional code with rate 1/n, measured in
bit per symbol, produces a coded sequence of n(L+M)
bits for a message of L bits and M stage sift register.
• Thus Code rate r=L/ n(L+M) bits/ symbol
• For L>>M, r 1/n
• Constraint length: number of shifts over which a single
message bit can influence encoder output. For M stage
shift register, constraint length is M+1
FFFF
Mod 2
adder
Convolutional coder
Constraint length 3, Rate =1/2
Impulse response
top adder output: (g0
(1), g1
(1), g1
(1)) =(1,1,1)
bottom adder output: (g0
(2), g1
(2), g1
(2))=(1,0,1)
convolution codes: Time domain approach
4/2/2018 14
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Let generator sequences of convolutional coder are
• Input top adder output: (g0
(1), g1
(1), g1
(1)) =(1,1,1)
• Input bottom adder output: (g0
(2), g1
(2), g1
(2))=(1,0,1)
And let message (m0,m1,m2,m3,m4)=(10011)
1 1
0
2 2
0
top output sequence 0,1,2,
bottom output sequence 0,1,2,
M
i l i l
l
M
i l i l
l
x g m i
x g m i




    
    


By calculating above convolution we get pair of outputs for message sequence as xi=(11,
10, 11, 11, 01, 01, 11)
Convolution codes: Transform domain
approach
4/2/2018 15
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Let generator sequences of convolutional coder are
• Input top adder output: g(1)(D)=1+D+D2
• Input bottom adder output: g(2)(D)=1+D2
• And let message is 10011 then m(D)= 1+D3+D4
• Then x1= g(1)(D) m(D) mod (D7-1)=(1+D+D2)(1+D3+D4)
x1= 1+D3+D4+D+D4+D5+D2+D5+D6
=(1111001)
• Then x2= g(2)(D) m(D) mod (D7-1)=(1+D2)(1+D3+D4)
x2= 1+D3+D4+D2+D5+D6
=(1011111)
Combining the two outputs we get pair of outputs for message sequence as xi=(11, 10, 11,
11, 01, 01, 11)
Convolutional coder: State diagram
4/2/2018 16
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Structural properties of a convolutional coder is given by one
of the three diagrams: Code tree, trellis and state diagram
With two FF’s, 4 possible states are Let a (00), b (10), c (01)
and d (11)
State table
FFFF
Constraint length 3, Rate =1/2
top output: g(1)=(1,1,1)
bottom output g(2)=(1,0,1)
state input Next state output
a 0 a 00
a 1 b 11
b 0 c 10
b 1 d 01
c 0 a 11
c 1 b 00
d 0 c 01
d 1 d 10
d
b c
a
0/00
1/10
1/11
0/10
1/00
0/11
1/01 0/01
State diagram
Convolutional coder: Code tree
4/2/2018 17
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
• Each branch of tree represent an input symbol, with
corresponding pair of output on the branch.
• Input ‘0’ specifies upper branch, while ‘1’ represents
lower branch
• repetitive after first three branches
• Represents all possible sequence, thus expands
b
c
d
a
b
c
d
a
b
c
d
a
b
c
d
a
b
a
d
c
b
a
d
c
a
b
c
d
a
b
a
00
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
00
11
10
01
11
00
01
10
00
11
10
01
11
00
01
10
01
10
11
00
10
01
00
11
00
11
10
01
11
FFFF
Constraint length 3, Rate =1/2
top output: g(1)=(1,1,1)
bottom output g(2)=(1,0,1)
Convolutional coder: Trellis diagram
4/2/2018 18
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
• trellis is representation which do not expand
• It uses state of the coder to represent all possible sequences
• It is compact: number of nodes at any level is 2k-1, k→
constraint length
FFFF
Constraint length 3, Rate =1/2
top output: g(1)=(1,1,1)
bottom output g(2)=(1,0,1)
a
b
c
d
00 00 00 00
11 11 11 11
10
01
10
01
10
01
11
00
11
00
10
01
10
01
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
Encode bit 11 10 11 11 01 01 11
Message bit 1 0 0 1 1 0 0
Viterbi and Sequential decoding
4/2/2018 19
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Decoding of convolutional codes can be categorized into two groups
• Sequential decoding –Fano coding
• Maximum likelihood decoding –Viterbi coding
a
b
c
d
00 00 00 00
11 11 11 11
10
01
10
01
10
01
11
00
11
00
10
01
10
01
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
Encode bit 11 10 11 11 01 01 11
Message bit 1 0 0 1 1 0 0
Sequential decoding - Fano Algorithm
4/2/2018 20
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
• First proposed by Wozencraft and improved by Fano.
• Fano coding operates on code tree (may be trellis) and It allows forward or backward
movement
• At each stage of decoding Fano coding retains only three information
• Current path
• Immediate predecessor path
• One of its successor path
• Based on the information Fano algorithm can move from its current state to either its
selected successor path or its predecessor path.
• It starts with the root node and tally with the output it finds on the way. If an output
does not matches, it retraces back to the previous ambiguous state.
Sequential decoding – Fano Algorithm
4/2/2018 21
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
a
b
c
d
00 00 00 00
11 11 11 11
10
01
10
01
10
01
11
00
11
00
10
01
10
01
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
00
10
01
11
Encode bit 11 10 11 11 01 01 11
Message bit 1 0 0 1 1 0 0
Received bit 11 10 11 10 01 01 11
Convolution decoding - Viterbi Algorithm
4/2/2018 22
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
• Developed by Andrew J. Viterbi who founded Qualcomm.
• Viterbi decoder examines entire received sequence of given length.
• Works on trellis diagram created level by level.
• Algorithm works by computing a ‘metric’ for each path.
• Metric is hamming distance between received bits and coded sequence of that path
• At any level, for each node, path with lower metric is retained (survivor path).
• If paths entering a node have equal metric, anyone may be retained.
• Small list of survivors are guaranteed to contain maximum likelihood choice
• If a condition arises that there is no path for the corresponding sequence then the
Viterbi decoding helps to detect the best path based on the subsequent sequence.
Sequential decoding – Fano Algorithm
4/2/2018 23
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Encode bit 11 10 11 11 01 01 11
Received bit 11 10 11 10 01 01 11
a
b
c
d
00
11
2
0
-
-
Received bit 11 Metric
a
b
c
d
00 00
11 11
10
01
11
00
10
01
0
2
3
3
Received bit 11 10 11 Metric
a
b
c
d
00 00
11 11
10
01
3
3
0
2
Received bit 11 10 Metric
Level 1 Level 2 Level 3
1
1
2
3
Received 11 10 11 10 Metric
bit
a
b
c
d
00 00
11 11
10
01
11
00
10
01
00
11
10
10
Level 4
2
2
3
1
Received 11 10 11 10 01 Metric
bit
a
b
c
d
00 00
11 11
10
01
11
00
10
01
00
11
10
10
00
11
10
01
Level 5
Sequential decoding – Fano Algorithm
4/2/2018 24
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
11
00
10
01
3
3
1
2
Received 11 10 11 10 01 01 Metric
bit
a
b
c
d
00 00
11 11
10
01
11
00
10
01
00
11
10
10
00
11
10
01
00
11
01
01
1
3
3
3
Received 11 10 11 10 01 01 11 Metric
bit
a
b
c
d
00 00
11 11
10
01
11
00
10
01
00
11
10
10
00
11
10
01
00
11
01
01
Received bit 11 10 11 11 01 01 11 Metric
Level 7
Level 7
Burst error correction
4/2/2018 25
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Burst errors are errors that occur in many consecutive bits rather than occurring in bits
independently of each other. Burst errors are localized in a short interval. methods to
correct random errors are inefficient to correct burst errors.
Examples:
• errors in CD, due to physical damage such as scratch on a disc
• Errors due to stroke of lightning in case of wireless channels.
Error vector E={010000110} is a burst of length 7. It can be said as cyclic burst of length 5
{11001}
Every (n,k) cyclic code with generator polynomial of degree r (=n-k) can detect all bursts
of length ≤r. However cyclic codes can detect most of the bursts of the length >r
Few points on Turbo codes
4/2/2018 26
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
Turbo codes are a class of high-performance FEC codes developed around 1990–91,
which closely approach the channel capacity, and are use to achieve reliable information
transfer in the presence of data-corrupting noise.
Applications:
• 3G/4G mobile communication ; ex. HSPA, EV-DO and LTE.
• satellite communication systems.
• NASA’s Mars Reconnaissance Orbiter use turbo codes,
• block /convolutional turbo coding are used in IEEE 802.16 (WiMAX)
Turbo codes are nowadays competing with LDPC codes, which provide similar
performance.
Few points on Turbo codes
4/2/2018 27
NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering,
JETGI, (JIT Jahangirabad)
The classic turbo encoder have two RSC
(Recursive systematic coder) and a bit
interleaver.
Encoder generates m bits of message X, n/2
bits of parity Y1 by RSC 1 and n/2 bits of
parity Y2 by RSC 2 thus generating m+n bits,
i.e. code rate is m/(m+n).
Permutation of payload data is carried by
interleaver.
Decoder of turbo coding is similar to that of
encoder
RSC
RSC
Interleaver
X
Y1 Y2
Input
Turbo encoder
Decoder 2Decoder 1X
Y1
Y2
Turbo decoder
Interleaver
Y
Ad

More Related Content

What's hot (20)

Line coding
Line codingLine coding
Line coding
Rina Ahire
 
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...
Madhumita Tamhane
 
Multirate DSP
Multirate DSPMultirate DSP
Multirate DSP
@zenafaris91
 
Source coding
Source coding Source coding
Source coding
Shankar Gangaju
 
Linear block coding
Linear block codingLinear block coding
Linear block coding
jknm
 
Convolutional Codes And Their Decoding
Convolutional Codes And Their DecodingConvolutional Codes And Their Decoding
Convolutional Codes And Their Decoding
Kakali Saharia
 
Digital Communication: Channel Coding
Digital Communication: Channel CodingDigital Communication: Channel Coding
Digital Communication: Channel Coding
Dr. Sanjay M. Gulhane
 
LDPC Codes
LDPC CodesLDPC Codes
LDPC Codes
Sahar Foroughi
 
BCH Codes
BCH CodesBCH Codes
BCH Codes
AakankshaR
 
DSP_2018_FOEHU - Lec 0 - Course Outlines
DSP_2018_FOEHU - Lec 0 - Course OutlinesDSP_2018_FOEHU - Lec 0 - Course Outlines
DSP_2018_FOEHU - Lec 0 - Course Outlines
Amr E. Mohamed
 
Diversity techniques presentation material
Diversity techniques presentation materialDiversity techniques presentation material
Diversity techniques presentation material
Nini Lashari
 
Sampling theorem
Sampling theoremSampling theorem
Sampling theorem
Shanu Bhuvana
 
Schelkunoff Polynomial Method for Antenna Synthesis
Schelkunoff Polynomial Method for Antenna SynthesisSchelkunoff Polynomial Method for Antenna Synthesis
Schelkunoff Polynomial Method for Antenna Synthesis
Swapnil Bangera
 
Z transfrm ppt
Z transfrm pptZ transfrm ppt
Z transfrm ppt
SWATI MISHRA
 
Error control coding techniques
Error control coding techniquesError control coding techniques
Error control coding techniques
DhanashriNandre
 
Subband Coding
Subband CodingSubband Coding
Subband Coding
Mihika Shah
 
LDPC - Low Density Parity Check Matrix
LDPC - Low Density Parity Check MatrixLDPC - Low Density Parity Check Matrix
LDPC - Low Density Parity Check Matrix
Kavi
 
Error Control Coding -Introduction
Error Control Coding -IntroductionError Control Coding -Introduction
Error Control Coding -Introduction
Burdwan University
 
Equalization
EqualizationEqualization
Equalization
@zenafaris91
 
FM demodulation using PLL
FM demodulation using PLLFM demodulation using PLL
FM demodulation using PLL
mpsrekha83
 
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...
Madhumita Tamhane
 
Linear block coding
Linear block codingLinear block coding
Linear block coding
jknm
 
Convolutional Codes And Their Decoding
Convolutional Codes And Their DecodingConvolutional Codes And Their Decoding
Convolutional Codes And Their Decoding
Kakali Saharia
 
Digital Communication: Channel Coding
Digital Communication: Channel CodingDigital Communication: Channel Coding
Digital Communication: Channel Coding
Dr. Sanjay M. Gulhane
 
DSP_2018_FOEHU - Lec 0 - Course Outlines
DSP_2018_FOEHU - Lec 0 - Course OutlinesDSP_2018_FOEHU - Lec 0 - Course Outlines
DSP_2018_FOEHU - Lec 0 - Course Outlines
Amr E. Mohamed
 
Diversity techniques presentation material
Diversity techniques presentation materialDiversity techniques presentation material
Diversity techniques presentation material
Nini Lashari
 
Schelkunoff Polynomial Method for Antenna Synthesis
Schelkunoff Polynomial Method for Antenna SynthesisSchelkunoff Polynomial Method for Antenna Synthesis
Schelkunoff Polynomial Method for Antenna Synthesis
Swapnil Bangera
 
Error control coding techniques
Error control coding techniquesError control coding techniques
Error control coding techniques
DhanashriNandre
 
LDPC - Low Density Parity Check Matrix
LDPC - Low Density Parity Check MatrixLDPC - Low Density Parity Check Matrix
LDPC - Low Density Parity Check Matrix
Kavi
 
Error Control Coding -Introduction
Error Control Coding -IntroductionError Control Coding -Introduction
Error Control Coding -Introduction
Burdwan University
 
FM demodulation using PLL
FM demodulation using PLLFM demodulation using PLL
FM demodulation using PLL
mpsrekha83
 

Similar to Error Control coding (20)

3320 cyclic codes.ppt
3320 cyclic codes.ppt3320 cyclic codes.ppt
3320 cyclic codes.ppt
AnkitGupta86532
 
M.TECH, ECE 2nd SEM LAB RECORD
M.TECH, ECE 2nd SEM LAB RECORD M.TECH, ECE 2nd SEM LAB RECORD
M.TECH, ECE 2nd SEM LAB RECORD
Arif Ahmed
 
Y03301460154
Y03301460154Y03301460154
Y03301460154
ijceronline
 
Channel Coding (Error Control Coding)
Channel Coding (Error Control Coding)Channel Coding (Error Control Coding)
Channel Coding (Error Control Coding)
Ola Mashaqi @ an-najah national university
 
Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...
Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...
Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...
IRJET Journal
 
02 ldpc bit flipping_decoding_dark knight
02 ldpc bit flipping_decoding_dark knight02 ldpc bit flipping_decoding_dark knight
02 ldpc bit flipping_decoding_dark knight
Devanshi Piprottar
 
Modified Golomb Code For Integer Representation
Modified Golomb Code For Integer RepresentationModified Golomb Code For Integer Representation
Modified Golomb Code For Integer Representation
IJSRD
 
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...
IJECEIAES
 
Defense Senior College on Error Coding presentation 4/22/2010
Defense Senior College on Error Coding presentation 4/22/2010Defense Senior College on Error Coding presentation 4/22/2010
Defense Senior College on Error Coding presentation 4/22/2010
Felicia Fort, MBA
 
Coding
CodingCoding
Coding
Dayal Sati
 
error control coding
error control coding error control coding
error control coding
Suhad Malayshi
 
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...
IOSR Journals
 
Unit-4.pptx
Unit-4.pptxUnit-4.pptx
Unit-4.pptx
4NM19EC140ROHITHUACH
 
FPGA based BCH Decoder
FPGA based BCH DecoderFPGA based BCH Decoder
FPGA based BCH Decoder
ijsrd.com
 
Belief Propagation Decoder for LDPC Codes Based on VLSI Implementation
Belief Propagation Decoder for LDPC Codes Based on VLSI ImplementationBelief Propagation Decoder for LDPC Codes Based on VLSI Implementation
Belief Propagation Decoder for LDPC Codes Based on VLSI Implementation
inventionjournals
 
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
VIT-AP University
 
Convolutional Codes.pdf
Convolutional Codes.pdfConvolutional Codes.pdf
Convolutional Codes.pdf
Jimma University
 
3F4ecc.ppten cje cen cne cdn en c e cnec cen
3F4ecc.ppten cje cen cne cdn en c e cnec cen3F4ecc.ppten cje cen cne cdn en c e cnec cen
3F4ecc.ppten cje cen cne cdn en c e cnec cen
dpsvngaur12217
 
3F4ecc.ppt
3F4ecc.ppt3F4ecc.ppt
3F4ecc.ppt
Annymus
 
G364246
G364246G364246
G364246
IJERA Editor
 
M.TECH, ECE 2nd SEM LAB RECORD
M.TECH, ECE 2nd SEM LAB RECORD M.TECH, ECE 2nd SEM LAB RECORD
M.TECH, ECE 2nd SEM LAB RECORD
Arif Ahmed
 
Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...
Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...
Review paper on Reed Solomon (204,188) Decoder for Digital Video Broadcasting...
IRJET Journal
 
02 ldpc bit flipping_decoding_dark knight
02 ldpc bit flipping_decoding_dark knight02 ldpc bit flipping_decoding_dark knight
02 ldpc bit flipping_decoding_dark knight
Devanshi Piprottar
 
Modified Golomb Code For Integer Representation
Modified Golomb Code For Integer RepresentationModified Golomb Code For Integer Representation
Modified Golomb Code For Integer Representation
IJSRD
 
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...
IJECEIAES
 
Defense Senior College on Error Coding presentation 4/22/2010
Defense Senior College on Error Coding presentation 4/22/2010Defense Senior College on Error Coding presentation 4/22/2010
Defense Senior College on Error Coding presentation 4/22/2010
Felicia Fort, MBA
 
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...
IOSR Journals
 
FPGA based BCH Decoder
FPGA based BCH DecoderFPGA based BCH Decoder
FPGA based BCH Decoder
ijsrd.com
 
Belief Propagation Decoder for LDPC Codes Based on VLSI Implementation
Belief Propagation Decoder for LDPC Codes Based on VLSI ImplementationBelief Propagation Decoder for LDPC Codes Based on VLSI Implementation
Belief Propagation Decoder for LDPC Codes Based on VLSI Implementation
inventionjournals
 
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
VIT-AP University
 
3F4ecc.ppten cje cen cne cdn en c e cnec cen
3F4ecc.ppten cje cen cne cdn en c e cnec cen3F4ecc.ppten cje cen cne cdn en c e cnec cen
3F4ecc.ppten cje cen cne cdn en c e cnec cen
dpsvngaur12217
 
3F4ecc.ppt
3F4ecc.ppt3F4ecc.ppt
3F4ecc.ppt
Annymus
 
Ad

More from Dr Naim R Kidwai (20)

Asynchronous sequential circuit analysis
Asynchronous sequential circuit analysisAsynchronous sequential circuit analysis
Asynchronous sequential circuit analysis
Dr Naim R Kidwai
 
synchronous Sequential circuit counters and registers
synchronous Sequential circuit counters and registerssynchronous Sequential circuit counters and registers
synchronous Sequential circuit counters and registers
Dr Naim R Kidwai
 
Clocked Sequential circuit analysis and design
Clocked Sequential circuit analysis and designClocked Sequential circuit analysis and design
Clocked Sequential circuit analysis and design
Dr Naim R Kidwai
 
Sequential circuit-flip flops
Sequential circuit-flip flopsSequential circuit-flip flops
Sequential circuit-flip flops
Dr Naim R Kidwai
 
Sampling Theorem
Sampling TheoremSampling Theorem
Sampling Theorem
Dr Naim R Kidwai
 
Moodle introduction
Moodle introductionMoodle introduction
Moodle introduction
Dr Naim R Kidwai
 
Project financial feasibility
Project financial feasibilityProject financial feasibility
Project financial feasibility
Dr Naim R Kidwai
 
financing infrastructure projects
financing infrastructure projectsfinancing infrastructure projects
financing infrastructure projects
Dr Naim R Kidwai
 
financing projects
financing projectsfinancing projects
financing projects
Dr Naim R Kidwai
 
multiple projects and constraints
multiple projects and constraintsmultiple projects and constraints
multiple projects and constraints
Dr Naim R Kidwai
 
project risk analysis
project risk analysisproject risk analysis
project risk analysis
Dr Naim R Kidwai
 
Nec 602 unit ii Random Variables and Random process
Nec 602 unit ii Random Variables and Random processNec 602 unit ii Random Variables and Random process
Nec 602 unit ii Random Variables and Random process
Dr Naim R Kidwai
 
spread spectrum communication
spread spectrum communicationspread spectrum communication
spread spectrum communication
Dr Naim R Kidwai
 
information theory
information theoryinformation theory
information theory
Dr Naim R Kidwai
 
Rec101 unit ii (part 2) bjt biasing and re model
Rec101 unit ii (part 2) bjt biasing and re modelRec101 unit ii (part 2) bjt biasing and re model
Rec101 unit ii (part 2) bjt biasing and re model
Dr Naim R Kidwai
 
Rec101 unit ii (part 3) field effect transistor
Rec101 unit ii (part 3) field effect transistorRec101 unit ii (part 3) field effect transistor
Rec101 unit ii (part 3) field effect transistor
Dr Naim R Kidwai
 
Rec101 unit ii (part 1) bjt characteristics
Rec101 unit ii (part 1) bjt characteristicsRec101 unit ii (part 1) bjt characteristics
Rec101 unit ii (part 1) bjt characteristics
Dr Naim R Kidwai
 
Rec101 unit v communication engg
Rec101 unit v communication enggRec101 unit v communication engg
Rec101 unit v communication engg
Dr Naim R Kidwai
 
Rec101 unit iv emi
Rec101 unit iv emiRec101 unit iv emi
Rec101 unit iv emi
Dr Naim R Kidwai
 
Rec101 unit iii operational amplifier
Rec101 unit iii operational amplifierRec101 unit iii operational amplifier
Rec101 unit iii operational amplifier
Dr Naim R Kidwai
 
Asynchronous sequential circuit analysis
Asynchronous sequential circuit analysisAsynchronous sequential circuit analysis
Asynchronous sequential circuit analysis
Dr Naim R Kidwai
 
synchronous Sequential circuit counters and registers
synchronous Sequential circuit counters and registerssynchronous Sequential circuit counters and registers
synchronous Sequential circuit counters and registers
Dr Naim R Kidwai
 
Clocked Sequential circuit analysis and design
Clocked Sequential circuit analysis and designClocked Sequential circuit analysis and design
Clocked Sequential circuit analysis and design
Dr Naim R Kidwai
 
Sequential circuit-flip flops
Sequential circuit-flip flopsSequential circuit-flip flops
Sequential circuit-flip flops
Dr Naim R Kidwai
 
Project financial feasibility
Project financial feasibilityProject financial feasibility
Project financial feasibility
Dr Naim R Kidwai
 
financing infrastructure projects
financing infrastructure projectsfinancing infrastructure projects
financing infrastructure projects
Dr Naim R Kidwai
 
multiple projects and constraints
multiple projects and constraintsmultiple projects and constraints
multiple projects and constraints
Dr Naim R Kidwai
 
Nec 602 unit ii Random Variables and Random process
Nec 602 unit ii Random Variables and Random processNec 602 unit ii Random Variables and Random process
Nec 602 unit ii Random Variables and Random process
Dr Naim R Kidwai
 
spread spectrum communication
spread spectrum communicationspread spectrum communication
spread spectrum communication
Dr Naim R Kidwai
 
Rec101 unit ii (part 2) bjt biasing and re model
Rec101 unit ii (part 2) bjt biasing and re modelRec101 unit ii (part 2) bjt biasing and re model
Rec101 unit ii (part 2) bjt biasing and re model
Dr Naim R Kidwai
 
Rec101 unit ii (part 3) field effect transistor
Rec101 unit ii (part 3) field effect transistorRec101 unit ii (part 3) field effect transistor
Rec101 unit ii (part 3) field effect transistor
Dr Naim R Kidwai
 
Rec101 unit ii (part 1) bjt characteristics
Rec101 unit ii (part 1) bjt characteristicsRec101 unit ii (part 1) bjt characteristics
Rec101 unit ii (part 1) bjt characteristics
Dr Naim R Kidwai
 
Rec101 unit v communication engg
Rec101 unit v communication enggRec101 unit v communication engg
Rec101 unit v communication engg
Dr Naim R Kidwai
 
Rec101 unit iii operational amplifier
Rec101 unit iii operational amplifierRec101 unit iii operational amplifier
Rec101 unit iii operational amplifier
Dr Naim R Kidwai
 
Ad

Recently uploaded (20)

Design Optimization of Reinforced Concrete Waffle Slab Using Genetic Algorithm
Design Optimization of Reinforced Concrete Waffle Slab Using Genetic AlgorithmDesign Optimization of Reinforced Concrete Waffle Slab Using Genetic Algorithm
Design Optimization of Reinforced Concrete Waffle Slab Using Genetic Algorithm
Journal of Soft Computing in Civil Engineering
 
Agents chapter of Artificial intelligence
Agents chapter of Artificial intelligenceAgents chapter of Artificial intelligence
Agents chapter of Artificial intelligence
DebdeepMukherjee9
 
Control Methods of Noise Pollutions.pptx
Control Methods of Noise Pollutions.pptxControl Methods of Noise Pollutions.pptx
Control Methods of Noise Pollutions.pptx
vvsasane
 
[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...
[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...
[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...
Jimmy Lai
 
Urban Transport Infrastructure September 2023
Urban Transport Infrastructure September 2023Urban Transport Infrastructure September 2023
Urban Transport Infrastructure September 2023
Rajesh Prasad
 
22PCOAM16 ML Unit 3 Full notes PDF & QB.pdf
22PCOAM16 ML Unit 3 Full notes PDF & QB.pdf22PCOAM16 ML Unit 3 Full notes PDF & QB.pdf
22PCOAM16 ML Unit 3 Full notes PDF & QB.pdf
Guru Nanak Technical Institutions
 
Deepfake Phishing: A New Frontier in Cyber Threats
Deepfake Phishing: A New Frontier in Cyber ThreatsDeepfake Phishing: A New Frontier in Cyber Threats
Deepfake Phishing: A New Frontier in Cyber Threats
RaviKumar256934
 
Construction Materials (Paints) in Civil Engineering
Construction Materials (Paints) in Civil EngineeringConstruction Materials (Paints) in Civil Engineering
Construction Materials (Paints) in Civil Engineering
Lavish Kashyap
 
Transport modelling at SBB, presentation at EPFL in 2025
Transport modelling at SBB, presentation at EPFL in 2025Transport modelling at SBB, presentation at EPFL in 2025
Transport modelling at SBB, presentation at EPFL in 2025
Antonin Danalet
 
Personal Protective Efsgfgsffquipment.ppt
Personal Protective Efsgfgsffquipment.pptPersonal Protective Efsgfgsffquipment.ppt
Personal Protective Efsgfgsffquipment.ppt
ganjangbegu579
 
OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...
OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...
OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...
ijdmsjournal
 
Understand water laser communication using Arduino laser and solar panel
Understand water laser communication using Arduino laser and solar panelUnderstand water laser communication using Arduino laser and solar panel
Understand water laser communication using Arduino laser and solar panel
NaveenBotsa
 
Automatic Quality Assessment for Speech and Beyond
Automatic Quality Assessment for Speech and BeyondAutomatic Quality Assessment for Speech and Beyond
Automatic Quality Assessment for Speech and Beyond
NU_I_TODALAB
 
Lecture - 7 Canals of the topic of the civil engineering
Lecture - 7  Canals of the topic of the civil engineeringLecture - 7  Canals of the topic of the civil engineering
Lecture - 7 Canals of the topic of the civil engineering
MJawadkhan1
 
DeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFT
DeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFTDeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFT
DeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFT
Kyohei Ito
 
Water Industry Process Automation & Control Monthly May 2025
Water Industry Process Automation & Control Monthly May 2025Water Industry Process Automation & Control Monthly May 2025
Water Industry Process Automation & Control Monthly May 2025
Water Industry Process Automation & Control
 
Mode-Wise Corridor Level Travel-Time Estimation Using Machine Learning Models
Mode-Wise Corridor Level Travel-Time Estimation Using Machine Learning ModelsMode-Wise Corridor Level Travel-Time Estimation Using Machine Learning Models
Mode-Wise Corridor Level Travel-Time Estimation Using Machine Learning Models
Journal of Soft Computing in Civil Engineering
 
VISHAL KUMAR SINGH Latest Resume with updated details
VISHAL KUMAR SINGH Latest Resume with updated detailsVISHAL KUMAR SINGH Latest Resume with updated details
VISHAL KUMAR SINGH Latest Resume with updated details
Vishal Kumar Singh
 
Optimizing Reinforced Concrete Cantilever Retaining Walls Using Gases Brownia...
Optimizing Reinforced Concrete Cantilever Retaining Walls Using Gases Brownia...Optimizing Reinforced Concrete Cantilever Retaining Walls Using Gases Brownia...
Optimizing Reinforced Concrete Cantilever Retaining Walls Using Gases Brownia...
Journal of Soft Computing in Civil Engineering
 
22PCOAM16 Unit 3 Session 23 Different ways to Combine Classifiers.pptx
22PCOAM16 Unit 3 Session 23  Different ways to Combine Classifiers.pptx22PCOAM16 Unit 3 Session 23  Different ways to Combine Classifiers.pptx
22PCOAM16 Unit 3 Session 23 Different ways to Combine Classifiers.pptx
Guru Nanak Technical Institutions
 
Agents chapter of Artificial intelligence
Agents chapter of Artificial intelligenceAgents chapter of Artificial intelligence
Agents chapter of Artificial intelligence
DebdeepMukherjee9
 
Control Methods of Noise Pollutions.pptx
Control Methods of Noise Pollutions.pptxControl Methods of Noise Pollutions.pptx
Control Methods of Noise Pollutions.pptx
vvsasane
 
[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...
[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...
[PyCon US 2025] Scaling the Mountain_ A Framework for Tackling Large-Scale Te...
Jimmy Lai
 
Urban Transport Infrastructure September 2023
Urban Transport Infrastructure September 2023Urban Transport Infrastructure September 2023
Urban Transport Infrastructure September 2023
Rajesh Prasad
 
Deepfake Phishing: A New Frontier in Cyber Threats
Deepfake Phishing: A New Frontier in Cyber ThreatsDeepfake Phishing: A New Frontier in Cyber Threats
Deepfake Phishing: A New Frontier in Cyber Threats
RaviKumar256934
 
Construction Materials (Paints) in Civil Engineering
Construction Materials (Paints) in Civil EngineeringConstruction Materials (Paints) in Civil Engineering
Construction Materials (Paints) in Civil Engineering
Lavish Kashyap
 
Transport modelling at SBB, presentation at EPFL in 2025
Transport modelling at SBB, presentation at EPFL in 2025Transport modelling at SBB, presentation at EPFL in 2025
Transport modelling at SBB, presentation at EPFL in 2025
Antonin Danalet
 
Personal Protective Efsgfgsffquipment.ppt
Personal Protective Efsgfgsffquipment.pptPersonal Protective Efsgfgsffquipment.ppt
Personal Protective Efsgfgsffquipment.ppt
ganjangbegu579
 
OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...
OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...
OPTIMIZING DATA INTEROPERABILITY IN AGILE ORGANIZATIONS: INTEGRATING NONAKA’S...
ijdmsjournal
 
Understand water laser communication using Arduino laser and solar panel
Understand water laser communication using Arduino laser and solar panelUnderstand water laser communication using Arduino laser and solar panel
Understand water laser communication using Arduino laser and solar panel
NaveenBotsa
 
Automatic Quality Assessment for Speech and Beyond
Automatic Quality Assessment for Speech and BeyondAutomatic Quality Assessment for Speech and Beyond
Automatic Quality Assessment for Speech and Beyond
NU_I_TODALAB
 
Lecture - 7 Canals of the topic of the civil engineering
Lecture - 7  Canals of the topic of the civil engineeringLecture - 7  Canals of the topic of the civil engineering
Lecture - 7 Canals of the topic of the civil engineering
MJawadkhan1
 
DeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFT
DeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFTDeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFT
DeFAIMint | 🤖Mint to DeFAI. Vibe Trading as NFT
Kyohei Ito
 
VISHAL KUMAR SINGH Latest Resume with updated details
VISHAL KUMAR SINGH Latest Resume with updated detailsVISHAL KUMAR SINGH Latest Resume with updated details
VISHAL KUMAR SINGH Latest Resume with updated details
Vishal Kumar Singh
 
22PCOAM16 Unit 3 Session 23 Different ways to Combine Classifiers.pptx
22PCOAM16 Unit 3 Session 23  Different ways to Combine Classifiers.pptx22PCOAM16 Unit 3 Session 23  Different ways to Combine Classifiers.pptx
22PCOAM16 Unit 3 Session 23 Different ways to Combine Classifiers.pptx
Guru Nanak Technical Institutions
 

Error Control coding

  • 1. Information Theory & Coding Unit V : Measure of Information, Source Encoding, Error Free Communication over a Noisy Channel capacity of a discrete and Continuous Memoryless channel Error Correcting codes: Hamming sphere, Hamming distance and Hamming bound, relation between minimum distance and error detecting and correcting capability, Linear block codes, encoding & syndrome decoding; Cyclic codes, encoder and decoders for systematic cycle codes; convolution codes, code tree & Trellis diagram, Viterbi and sequential decoding, burst error correction, Turbo codes. 4/2/2018 1 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad)
  • 2. Error Correcting Coding 4/2/2018 2 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) In Digital Communication, two important parameters in design are SNR Eb/No and bandwidth B and objective is to achieve acceptable reliability (error rate) of transmission. For a given Eb/No only coding (adding systematic redundancy) can ensure acceptable error rate of transmission. Error Control can be done by • FEC: forward error correction (Error detection and correction) • ARQ: Automatic request for retransmission (Error detection) Error control coding is systematic addition redundancy for error detection and correction.
  • 3. Hamming sphere, Hamming distance, Hamming weight, Hamming bound, and error correcting capability 4/2/2018 3 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Let a pair of code vectors are x and y that have same number of elements • Hamming distance d(x,y) between such pair of code vectors is defined as number of locations in which their respective locations. • Hamming weight w(x) of a code vector x is defined as the number of non zero elements of the code vector • Minimum distance dmin of linear code block is smallest hamming distance between any pair of code vectors in the code. • For the (n,k) linear block code, to be able to correct upto t bits of error (all error patterns of t bits or less) if and only if d(xi, xj) ≤ 2t+1 for all xi and xj • Hamming bound (n,k) block code can correct upto t errors provided Hamming bound is satisfied. For equality code is said to be perfect 0 2 t n k i n i          
  • 4. Linear Block Codes 4/2/2018 4 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) (n,k) linear block has n code bits of which consists of k message bits and n-k parity bits. b0, b1, ------------------, bn-k-1, m0, m1, ------------------, mk-1, N-k Parity bits K Message bits ,0 ,1 1 , 1 1 0,1, , 1 code where are parity bits and are message bits , 1, , 1 parity bits (all arithmatic in coding are modulo 2 i i i i i k n i i o i i k k b i n k x b m m i n k n k n b p m p m p m                              , 0 1 1 0 1 1 k k operations) 1 if depends on where 0 otherwise Let message [ , , ] and parity [ , , ] code [ ] [ ] [ I ] Let us define Generator Matrix =[ I ] i j i j k k b m p m m m m b b b b m p x b m m p m m p G p                  
  • 5. Linear Block Codes 4/2/2018 5 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) n-k n-k n-k n-k n-k then code vector Let us define parity cheker Matrix =[I ] then = I I I 0= I Again received vector = + where e is error vector added due to noise Synd T T T T T T T x m G H p p HG p p p GH y x e               rome = + [ 0]T T T T s y H x e H eH GH   • Syndrome depends on error pattern and not on codeword sent • All error pattern that differs by a codeword have same syndrome • A syndrome is sum of those columns of parity check matrix corresponding to error location • (n,k) block code can correct upto t errors provided Hamming bound is satisfied. • A code (n,k) is said to be perfect, if equality holds in Hamming bound
  • 6. Cyclic codes 4/2/2018 6 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Cyclic codes are subclass of linear block codes and are easy to encode. A cyclic code exhibits • Linearity property: Sum of two codewords is also a codeword. • Cyclic property: Cyclic shift of any codeword is also a codeword. If (x0, x1,--- xn-1) is codeword of (n,k) linear block code and is cyclic then (xn-1, x0,--- xn-2) (xn-2, xn-1,--- xn-3) . . (x1, x2,----- x0) are all valid codewords
  • 7. Cyclic codes 4/2/2018 7 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Codeword polynomial for code (x0, x1,-- ,xn-1) is codeword is written as x(D)= x0+ x1D+x2D+--------+ xn-1Dn-1 where D is a real variable, s.t Dn =1 The condition Dn =1 ensures • Codeword polynomial is of the order n-1 for a multiplication with D • Multiplication by D to the polynomial makes circular right shift • This leads to multiplication modulo Dn -1 D x(D) modulo (Dn-1) = xn-1+ x0D+x1D2+--------+ xn-2Dn-1 D2 x(D) modulo (Dn-1) = xn-2+ xn-1D+x0D2+--------+ xn-2Dn-1 Di x(D) modulo (Dn-1) is codeword polynomial for a cyclic shift i.
  • 8. Cyclic codes 4/2/2018 8 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Generator Polynomial g(D) g(D) is a factor of (Dn+1) having minimum degree n-k X(D)= a(D) g(D) modulo (Dn-1) where a(D) is polynomial Encoding Procedure: • Multiply message polynomial m(D) by Dn-k • Divide Dn-k m(D) by g(D) and obtain remainder b(D) • Add b(D) Dn-k m(D) giving codeword Parity Check polynomial h(D) h(D) g(D) modulo (Dn-1)=0 [like HGT=0] or h(D) g(D) =Dn+1
  • 9. Cyclic codes 4/2/2018 9 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) (7,4) Hamming Code Ex. 1+Dn= (1+D)(1+D2+D3)(1+D+D3) Let g(D)= 1+D+D3 then h(D)= (1+D)(1+D2+D3)= 1+D+D2+D3+D3+D4=1+D+D2+D4 G matrix can be constructed using g(D)= 1+ D+0D2+ D3+0D4+0D5+0D6 Dg(D)= 0+ D+ D2+0D3+ D4+0D5+0D6 D2g(D)=0+0D+ D2+ D3+0D4+ D5+0D6 D3g(D)=0+0D+0D2+ D3+ D4+0D5+ D6 1 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 G             1 1 0 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 1 0 0 0 1 G             G can be made systematic by using row operations make 4x4 identity matrix in last columns R3→R3+R1 and R4→R1+R2 +R4
  • 10. Encoder for Cyclic codes: Ex. (7,4) Hamming Code Encoder 4/2/2018 10 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Let g(D)= 1+D+D3 Then encoder can be easily made using Flip Flops as shown in figure It requires 3 FF, input/ output to each FF is marked. mod 2 addition is done for terms. For message 1001 Parity bits generated are 011 Code : 0111001 FFFFFF Gate D0=1 D D2 D3 message bits Parity bits Encoded bits Shift input Register output 0 0 0 1 1 1 1 0 2 0 0 1 1 3 0 1 1 1 4 1 0 1 1
  • 11. Syndrome calculation for Cyclic codes: Ex. (7,4) Hamming Code Syndrome 4/2/2018 11 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Let g(D)= 1+D+D3 Then parity checker (syndrome) can be made using Flip Flops as shown in figure It requires 3 FF, input/ output to each FF is marked. mod 2 addition is done for terms. For message 1001, Parity is 011 Transmitted Code: 0111001 If received vector : 0111001 Syndrome 000 No error If received vector : 0110001 Syndrome 110 error vector 0001000 Shift input Register output 0 0 0 1 1 1 0 0 2 0 0 1 0 3 0 0 0 1 4 1 0 1 0 5 1 1 0 1 6 1 0 0 0 7 0 0 0 0 FFFFFF Gate D0=1 D D2 D3 Syndrome for no error Shift input Register output 0 0 0 1 1 1 0 0 2 0 0 1 0 3 0 0 0 1 4 0 1 1 0 5 1 1 1 1 6 1 0 0 1 7 0 1 1 0 Syndrome for error vector 0001000
  • 12. Important cyclic codes 4/2/2018 12 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) • Cyclic Redundancy check codes (CRC): ▪ (18,6) CRC-12 g(D)=1+D+D2+D3+D11+D12 ▪ (24,8) CRC-16 g(D)=1+D2+D15+D16 ▪ (24,8) CRC-CCITT g(D)=1+D5+D12+D16 • Golay codes: Three error correcting perfect cyclic code ▪ (23,12) g(D)=1+D+D5+D6+D7+D9+D11 • Bose- Chaudhuri Hocquenqhem (BCH): ▪ Each BCH code is t error correcting code ▪ (15,7) 2 error corrrection g(D)=1+D4+D6+D7+D8
  • 13. convolution codes 4/2/2018 13 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) • Block codes are produced on block by block basis, thus requires a buffer. • For serial inputs, convolutional codes are preferred • Convolution coding operates on serial incoming bits • A binary convolutional code with rate 1/n, measured in bit per symbol, produces a coded sequence of n(L+M) bits for a message of L bits and M stage sift register. • Thus Code rate r=L/ n(L+M) bits/ symbol • For L>>M, r 1/n • Constraint length: number of shifts over which a single message bit can influence encoder output. For M stage shift register, constraint length is M+1 FFFF Mod 2 adder Convolutional coder Constraint length 3, Rate =1/2 Impulse response top adder output: (g0 (1), g1 (1), g1 (1)) =(1,1,1) bottom adder output: (g0 (2), g1 (2), g1 (2))=(1,0,1)
  • 14. convolution codes: Time domain approach 4/2/2018 14 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Let generator sequences of convolutional coder are • Input top adder output: (g0 (1), g1 (1), g1 (1)) =(1,1,1) • Input bottom adder output: (g0 (2), g1 (2), g1 (2))=(1,0,1) And let message (m0,m1,m2,m3,m4)=(10011) 1 1 0 2 2 0 top output sequence 0,1,2, bottom output sequence 0,1,2, M i l i l l M i l i l l x g m i x g m i                 By calculating above convolution we get pair of outputs for message sequence as xi=(11, 10, 11, 11, 01, 01, 11)
  • 15. Convolution codes: Transform domain approach 4/2/2018 15 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Let generator sequences of convolutional coder are • Input top adder output: g(1)(D)=1+D+D2 • Input bottom adder output: g(2)(D)=1+D2 • And let message is 10011 then m(D)= 1+D3+D4 • Then x1= g(1)(D) m(D) mod (D7-1)=(1+D+D2)(1+D3+D4) x1= 1+D3+D4+D+D4+D5+D2+D5+D6 =(1111001) • Then x2= g(2)(D) m(D) mod (D7-1)=(1+D2)(1+D3+D4) x2= 1+D3+D4+D2+D5+D6 =(1011111) Combining the two outputs we get pair of outputs for message sequence as xi=(11, 10, 11, 11, 01, 01, 11)
  • 16. Convolutional coder: State diagram 4/2/2018 16 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Structural properties of a convolutional coder is given by one of the three diagrams: Code tree, trellis and state diagram With two FF’s, 4 possible states are Let a (00), b (10), c (01) and d (11) State table FFFF Constraint length 3, Rate =1/2 top output: g(1)=(1,1,1) bottom output g(2)=(1,0,1) state input Next state output a 0 a 00 a 1 b 11 b 0 c 10 b 1 d 01 c 0 a 11 c 1 b 00 d 0 c 01 d 1 d 10 d b c a 0/00 1/10 1/11 0/10 1/00 0/11 1/01 0/01 State diagram
  • 17. Convolutional coder: Code tree 4/2/2018 17 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) • Each branch of tree represent an input symbol, with corresponding pair of output on the branch. • Input ‘0’ specifies upper branch, while ‘1’ represents lower branch • repetitive after first three branches • Represents all possible sequence, thus expands b c d a b c d a b c d a b c d a b a d c b a d c a b c d a b a 00 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 00 11 10 01 11 00 01 10 00 11 10 01 11 00 01 10 01 10 11 00 10 01 00 11 00 11 10 01 11 FFFF Constraint length 3, Rate =1/2 top output: g(1)=(1,1,1) bottom output g(2)=(1,0,1)
  • 18. Convolutional coder: Trellis diagram 4/2/2018 18 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) • trellis is representation which do not expand • It uses state of the coder to represent all possible sequences • It is compact: number of nodes at any level is 2k-1, k→ constraint length FFFF Constraint length 3, Rate =1/2 top output: g(1)=(1,1,1) bottom output g(2)=(1,0,1) a b c d 00 00 00 00 11 11 11 11 10 01 10 01 10 01 11 00 11 00 10 01 10 01 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 Encode bit 11 10 11 11 01 01 11 Message bit 1 0 0 1 1 0 0
  • 19. Viterbi and Sequential decoding 4/2/2018 19 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Decoding of convolutional codes can be categorized into two groups • Sequential decoding –Fano coding • Maximum likelihood decoding –Viterbi coding a b c d 00 00 00 00 11 11 11 11 10 01 10 01 10 01 11 00 11 00 10 01 10 01 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 Encode bit 11 10 11 11 01 01 11 Message bit 1 0 0 1 1 0 0
  • 20. Sequential decoding - Fano Algorithm 4/2/2018 20 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) • First proposed by Wozencraft and improved by Fano. • Fano coding operates on code tree (may be trellis) and It allows forward or backward movement • At each stage of decoding Fano coding retains only three information • Current path • Immediate predecessor path • One of its successor path • Based on the information Fano algorithm can move from its current state to either its selected successor path or its predecessor path. • It starts with the root node and tally with the output it finds on the way. If an output does not matches, it retraces back to the previous ambiguous state.
  • 21. Sequential decoding – Fano Algorithm 4/2/2018 21 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) a b c d 00 00 00 00 11 11 11 11 10 01 10 01 10 01 11 00 11 00 10 01 10 01 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 Encode bit 11 10 11 11 01 01 11 Message bit 1 0 0 1 1 0 0 Received bit 11 10 11 10 01 01 11
  • 22. Convolution decoding - Viterbi Algorithm 4/2/2018 22 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) • Developed by Andrew J. Viterbi who founded Qualcomm. • Viterbi decoder examines entire received sequence of given length. • Works on trellis diagram created level by level. • Algorithm works by computing a ‘metric’ for each path. • Metric is hamming distance between received bits and coded sequence of that path • At any level, for each node, path with lower metric is retained (survivor path). • If paths entering a node have equal metric, anyone may be retained. • Small list of survivors are guaranteed to contain maximum likelihood choice • If a condition arises that there is no path for the corresponding sequence then the Viterbi decoding helps to detect the best path based on the subsequent sequence.
  • 23. Sequential decoding – Fano Algorithm 4/2/2018 23 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Encode bit 11 10 11 11 01 01 11 Received bit 11 10 11 10 01 01 11 a b c d 00 11 2 0 - - Received bit 11 Metric a b c d 00 00 11 11 10 01 11 00 10 01 0 2 3 3 Received bit 11 10 11 Metric a b c d 00 00 11 11 10 01 3 3 0 2 Received bit 11 10 Metric Level 1 Level 2 Level 3 1 1 2 3 Received 11 10 11 10 Metric bit a b c d 00 00 11 11 10 01 11 00 10 01 00 11 10 10 Level 4 2 2 3 1 Received 11 10 11 10 01 Metric bit a b c d 00 00 11 11 10 01 11 00 10 01 00 11 10 10 00 11 10 01 Level 5
  • 24. Sequential decoding – Fano Algorithm 4/2/2018 24 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) 11 00 10 01 3 3 1 2 Received 11 10 11 10 01 01 Metric bit a b c d 00 00 11 11 10 01 11 00 10 01 00 11 10 10 00 11 10 01 00 11 01 01 1 3 3 3 Received 11 10 11 10 01 01 11 Metric bit a b c d 00 00 11 11 10 01 11 00 10 01 00 11 10 10 00 11 10 01 00 11 01 01 Received bit 11 10 11 11 01 01 11 Metric Level 7 Level 7
  • 25. Burst error correction 4/2/2018 25 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Burst errors are errors that occur in many consecutive bits rather than occurring in bits independently of each other. Burst errors are localized in a short interval. methods to correct random errors are inefficient to correct burst errors. Examples: • errors in CD, due to physical damage such as scratch on a disc • Errors due to stroke of lightning in case of wireless channels. Error vector E={010000110} is a burst of length 7. It can be said as cyclic burst of length 5 {11001} Every (n,k) cyclic code with generator polynomial of degree r (=n-k) can detect all bursts of length ≤r. However cyclic codes can detect most of the bursts of the length >r
  • 26. Few points on Turbo codes 4/2/2018 26 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) Turbo codes are a class of high-performance FEC codes developed around 1990–91, which closely approach the channel capacity, and are use to achieve reliable information transfer in the presence of data-corrupting noise. Applications: • 3G/4G mobile communication ; ex. HSPA, EV-DO and LTE. • satellite communication systems. • NASA’s Mars Reconnaissance Orbiter use turbo codes, • block /convolutional turbo coding are used in IEEE 802.16 (WiMAX) Turbo codes are nowadays competing with LDPC codes, which provide similar performance.
  • 27. Few points on Turbo codes 4/2/2018 27 NEC 602 by Dr Naim R Kidwai, Professor, F/o Engineering, JETGI, (JIT Jahangirabad) The classic turbo encoder have two RSC (Recursive systematic coder) and a bit interleaver. Encoder generates m bits of message X, n/2 bits of parity Y1 by RSC 1 and n/2 bits of parity Y2 by RSC 2 thus generating m+n bits, i.e. code rate is m/(m+n). Permutation of payload data is carried by interleaver. Decoder of turbo coding is similar to that of encoder RSC RSC Interleaver X Y1 Y2 Input Turbo encoder Decoder 2Decoder 1X Y1 Y2 Turbo decoder Interleaver Y
  翻译: