Design & Simulation With Verilog

Semi Design
Presents
Design & Simulation
of Digital Circuits
With
Verilog HDL
1
Mrs. K. Priya
Senior Design & Verification Engineer
Semi Design
info@semidesign.in www.semidesign.in
04-10-2020 Semi Design

Why not fresher's!!!
Before applying for VLSI job you must be able to answer
following questions
• Do you know about VLSI industry ?
• What are the different fields and areas are there in VLSI
industry?
• Which profile you are interested in the VLSI industry?
• What are the different tools you have worked with?
• What are the projects you have done?

VLSI achievement
3
 1st camera  Camera

4
 1st computer ,hard drive 5MB in
1956
 Laptop with 1TB hard-drive now a
days

5
Mobile phone used in 1980 used only
for communication purpose.
Mobile phones now a days used for
multipurpose.

What is VLSI
• Very Large Scale Integration ( Within IC).
• In 1965, Gordon E. Moore, the co-founder of Intel, made this
observation that became Moore's Law.
• Moore's Law states that the number of transistors on a
microchip doubles about every two years, though the cost of
computers is halved.
• Another tenet of Moore's Law says that the growth of
microprocessors is exponential.

How much large?
• SSI(Small Scale Integration ) : 10–100 transistors/chip or 3 - 30 gates
/chip(logic gates, flip flops)
• MSI(Medium Scale Integration ) :100–1000 transistors/chip or 30 -
300 gates /chip( counters, multiplexers, registers)
• LSI(Large Scale Integration ) : 1000–10,000 transistors/chip or 300 -
3000 gates /chip(8 bit processors)
• VLSI( Very Large Scale Integration ) :10,000–1,00,000
transistors/chip or morethan 3000 gates /chip.(16 bit and 32 bit
processors) (most popular)
• ULSI( Ultra Large Scale Integration ) :10power 6 –10 power 7
transistors/chip(smart sensors,VR reality modules)

VLSI design flow

Cont.
• Specifications:- According to customer demand (Ex: mobile
(low power consumption, high speed, good camera quality,
good video quality, higher memory etc.).
• Architecture design:-
The architecture team will design an architecture ( block
diagram having memories, processor, other design, how they are
connected (using all details in the specification) .This architecture
team will estimate the block area, how much power is required
and cost for the design.

Cont.
• RTL design:-
Register transfer level(RTL) .The above architecture is
converted into HDL (Hardware Description Language) code. This
code describes how data is transformed as it is passed from register
to register
• RTL verification:-
After the RTL design by applying test cases we verify the design in
verification stage (takes 60% of total time).If any mistakes are found
then the design is resend to the RTL designing department.

Cont…
• Synthesis:-
It is a process of converting the RTL code into gate level
netlist(generating hardware from code).Up to RTL verification the
design is technology independent. In synthesis process the
design is converted into technology dependent (what technology
you are using for transistors).
1.Translation:- The RTL code is converted in to
Boolean expression.
2.Optimization:- In this stage Boolean expression is optimized by
SOP and POS optimization method.
3.Mapping:- In this technology independent Boolean expression
is converted into technology dependent and generates the gate
level net list.

Cont.
• DFT:-
Design for testability(DFT) is a technique used to test after
production.
• Floorplan:-
It is the process of placing blocks/macros in the chip/core
area there by determining routing areas between them.
• Placement:-
Placement is the process of automatically assigning correct
position to standard cells on the chip with no overlapping.

Cont.
• CTS (clock tree synthesis):-
In the chip clock signal is essential to the flip flops, to give
the clock signal from clock source we built the clock tree. It is the
process of balancing the clock skew and minimizing insertion
delay in order to meet timing and power.
• Routing:- In this stage we connect all the cells with the metal
straps.
• Signoff:- In signoff stage all the tests are done to check the
quality and performance of the layout before tape out.

Cont.
• Fabrication:-
By the GDS II file information we fabricate the chip.
The total design is converted into chip by the manufacturing
process.
• Packaging and testing:-
After the fabrication process we test the chip. If there is
any fault in the design then we modifies the design by repeating
the steps. If there are no faults then chip will go to packaging.

MCQ
Qs1:-The design flow of VLSI system is
1. architecture design 2. market requirement 3. logic design 4.
HDL coding
a) 2-1-3-4
b) 4-1-3-2
c) 3-2-1-4
d) 1-2-3-4
Qs2:-The full form of VLSI is-
a) Very Long Single Integration
b) Very Least Scale Integration
c) Very Large Scale Integration
d) Very Long Scale Integration
•04-10-2020 Semi Design 16

FPGA
• FPGA stands for Field Programmable Gate Array.
• It is an integrated circuit which can be “field” programmed to
work as per the intended design.
• It means it can work as a microprocessor, or as an encryption
unit, or graphics card, or even all these three at once.
• The designs running on FPGAs are generally created using
hardware description languages .
• FPGA is made up of thousands of Configurable Logic Blocks
(CLBs) embedded in an ocean of programmable
interconnects.
• The CLBs are primarily made of Look-Up Tables (LUTs),
Multiplexers and Flip-Flops. They can implement complex
logic functions.
04-10-2020 Semi Design 17

ASIC
• ASIC stands for Application Specific Integrated Circuit.
• As the name implies, ASICs are application specific. They are
designed for one sole purpose and they function the same
their whole operating life.
• For example, the CPU inside your phone is an ASIC. It is meant
to function as a CPU for its whole life. The logic function of
ASIC is specified using hardware description languages .
• The difference in case of ASIC is that the resultant circuit is
permanently drawn into silicon whereas in FPGAs the circuit is
made by connecting a number of configurable blocks

What to prepare?
• Front end :
• As a fresher you can join as RTL design engineer or a
Verification engineer.
• you can gain deeper knowledge and skills as progress in
career.
• In terms of job opportunities, there is opportunity for more
verification engineers compared to design engineers.
• Back end
• As a fresher you can start with logic synthesis, Placement and
Routing , Layout, Physical verification, static timing analysis.
• Should have a better understanding in process
technologies, transistors, high speed design issues etc.

Knowledge for front end VLSI
• Good understanding on all the concepts of digital
electronics ( combinational & Sequential Circuits, Logic gates
and Finite State machine).
• Full understanding on the complete ASIC flow and all its
related steps.
• Proficient with the coding of VHDL/Verilog(Verilog is mostly
used).
• Sound knowledge on the Timing Analysis(STA) and all its
related concepts.

Cont.
• Good understanding and proficient with the coding of System
Verilog(Only for ASIC Verification) and knowledge on building
verification Environment using Methodologies like UVM.
• At least one of the scripting language either TCL(Back end) or
Perl or Python(front end).
• Good understanding on the protocols like APB,
AHB,AXI,I2C,UART etc.

Tools for front end VLSI
22
• Logic Simulation:
• Mentor Graphics :-Modelsim (free) or QuestaSim)
• Cadence:-ncvlog, ncelab, ncsimor nclaunch
• Synopsys :-vcs
• Logic Synthesis
• Mentor Graphics :-Leonardo or precision
• Cadence :-rc-complier
• Synopsys :-design compiler (dc)

Some list of VLSI companies
in India
• Product Companies – These companies designs and develops
ASICs, SOC, Microprocessors (Intel, NVidia, Qualcomm, AMD,
Samsung, MediaTek, Broadcom, TI, ST)
• Service Companies – These companies work on
outsourced/In-house project development for major product
companies. (Wipro, TCS, Tata Elxsi, Mirafra, Waferspace,
Sasken, Mindtree and many more)
• EDA (Electronic Design Automation) Companies – These
companies build the tools that are essential for various chip
design methodologies (Synopsys, Cadence, Mentor Graphics,
Aldec)

Cont.
• IP Design Companies – These companies focus on building
and selling IP (Intellectual property) for others.(ARM, MIPS
(Processor core), Synopsys, Cadence etc (Memories, Protocol
agents, connectivity)
• Fabrication (Fab) Companies – These are the companies that
focus on the manufacturing, packaging and other
aspects.(TSMC, Global Foundries, Samsung)

Follow these steps
• Increase your knowledge about the VLSI industry.
• Read Blogs related to VLSI.
• Attend different Seminars / Conferences which are related to
VLSI /Semiconductors.
• Become part of different groups/forums in social network and
try to understand what other people are discussing.
• Decide your area of interest , fix your goal. Start preparing
from now, to achieve your goal.

MCQ
Qs1:-Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
e) None of above
Qs2:-On which factor/s does the clock pulse frequency of a counter
depend/s for its reliable operation?
a) Number of flip flops
b) Width of strobe pulse
c) Propagation delay
d) All of the above
e) None of above

Why Digital??
• Easy to design.
• Storage is easy.
• Less influence of noise.
• Transmitted over long distance.
• can be programmable.
• High speed data transmission
• Ease of design.

Why HDL?
28
• If something goes wrong which one is easy to analyse?
• Which one have less no of components?
• Which one will have less no of code lines?

Cont.
• You can specify digital systems much faster than drawing the
complete schematics.
• The debug cycle is also often much faster.
• Modifications require code changes instead of schematic
rewiring.
• HDLs are used for both simulation and synthesis.
• Two types of HDL are accepted by IEEE. VHDL and Verilog.

VHDL
• Very High Speed Integrated Circuit (VHSIC) HDL developed by
United States government's department of defence (1981)
and rights where given to IEEE in 1986 became a standard and
published in 1987.
• Standard language used to describe digital hardware devices,
systems and components
• Revised standard published in 1993 (VHDL 1076-1993)
regulated by VHDL international (VI)

Verilog
• Verilog Hardware Description Language (HDL) was designed
and implemented by Phil Moorby & Prabhu Goel at Gateway
Design Automation in 1984
• Verilog became IEEE standard in December, 1995

Dataflow: Specify output signals in
terms of input signals
assign out = (sel & a) | (~sel & b);
33
sel
b
a
out
sel_n
sel_b
sel_a
Gate level: Logic is described in terms of
Verilog gate primitives.
Example:
not n1(sel_n, sel);
and a1(sel_b, b, sel_b);
and a2(sel_a, a, sel);
or o1(out, sel_b, sel_a);
sel
b
a
out
sel_n
sel_b
sel_a
n1
a1
a2
o1
Types of modelling

Behavioural Modelling
• Behavioral: Algorithmically specify the
behavior of the design.
if (select == 0) out = b;
else if (select == 1)
out = a;

Switch level modelling

Note
• The most important thing to remember when you are writing
HDL code is that you are describing real hardware, not writing a
computer program.
• If you don't know what hardware you are implying, you are
almost certain not to get what you want.

Verilog Code for 1-bit full adder

Cont.
• Simulators let you check the values of signals inside your system.

Cont.
• Synthesis converts the HDL code into digital logic circuits/ net-list / hardware.

MCQ
Qs1:Register transfer level description specifies all of the
registers in a design & ______ logic between them.
a. Sequential
b. Combinational
c. Both a and b
d. None of the above
Qs2:Which among the following is a process of transforming RTL
to gate level netlist?
a. Simulation
b. Optimization
c. Synthesis
d. Verification04-10-2020 Semi Design 40

Verilog – test bench
41
A setup for applying test vectors to test a design.

Cont.
• A test bench is written in another Verilog file.
• All the Verilog constructs used plan in your hardware design
must be synthesizable, meaning it has a hardware equivalent.
• The Verilog you write in a test bench does not need to be
synthesizable because you will only simulate it.
• Test benches are used to simulate the design without the need
of any physical hardware.

Cont.
• The biggest benefit of this is that you can actually check every
signal that is in your design.
• This definitely can be a time saver when your alternatives are
staring at the code, or loading it onto the FPGA and probing the
few signals brought out to the external pins.
• However, before you can simulate your design you must first
write a test bench.

44
Example of 4-bit ADDER

45
Test bench

Test-Bench Result

Thanks !!
Any Query ??

Design & Simulation With Verilog

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