Computer organisation Module 1.ppt

Computer
Organization
18CS34
1

2
Computer Organization
Course Learning Objectives
This course (18CS34) will enable students to:
 Explain the basic sub systems of a computer, their
organization, structure and operation.
 Illustrate the concept of programs as sequences of machine
instructions.
 Demonstrate different ways of communicating with I/O
devices and standard I/O interfaces.
 Describe memory hierarchy.
 Describe arithmetic and logical operations with integer and
floating-point operands.
 Illustrate organization of a simple processor, pipelined
processor and other computing systems.

3
Computer Organization
Course Outcomes
This course (18CS34) will enable students to:
 Explain the basic organization of a computer system.
 Demonstrate functioning of different sub systems, such
as processor, Input/output and memory.
 Illustrate hardwired control and micro programmed
control, pipelining, embedded and other computing
systems.
 Design and analyse simple arithmetic and logical units.

Module-1.
Basic Structure of Computers,
Machine Instructions and
Programs
4

 Text Books:
 Carl Hamacher, Zvonko Vranesic, Safwat Zaky:
Computer Organization, 5th Edition, Tata McGraw
Hill, 2002.
 Carl Hamacher, Zvonko Vranesic, Safwat Zaky,
Naraig Manjikian : Computer Organization and
Embedded Systems, 6th Edition, Tata McGraw Hill,
2012.
 Reference Books:
 William Stallings: Computer Organization &
Architecture, 9th Edition, Pearson, 2015.
5

The Computer Revolution
 Progress in computer technology
 Underpinned by Moore’s Law
 Makes novel applications feasible
 Computers in automobiles
 Cell phones
 Human genome project
 World Wide Web
 Search Engines
 Computers are universal
6

Classes of Computers
 Desktop/laptop computers
 General purpose, variety of software
 Subject to cost/performance tradeoff
 Workstations
 More computing power used in engg. applications, graphics etc.
 Enterprise System/ Mainframes
 Used for business data processing
 Server computers (Low End Range)
 Network based
 High capacity, performance, reliability
 Range from small servers to building sized
 Supercomputer (High End Range)
 Large scale numerical calculation such as weather forecasting, aircraft
design
 Embedded computers
 Hidden as components of systems
 Stringent power/performance/cost constraints
7

What You Will Learn
 How programs are translated into the
machine language
 And how the hardware executes them
 The hardware/software interface
 What determines program performance
 And how it can be improved
 How hardware designers improve
performance
8

Understanding Performance
 Algorithm
 Determines number of operations executed
 Programming language, compiler, architecture
 Determine number of machine instructions executed
per operation
 Processor and memory system
 Determine how fast instructions are executed
 I/O system (including OS)
 Determines how fast I/O operations are executed
9

Functional Units
11
Figure 1.1. Basic functional units of a computer.
I/O Processor
Output
Memory
Input and
Arithmetic
logic
Control

Information Handled by a
Computer
 Instructions/machine instructions
 Govern the transfer of information within a computer as
well as between the computer and its I/O devices
 Specify the arithmetic and logic operations to be
performed
 Program
 Data
 Used as operands by the instructions
 Source program
 Encoded in binary code – 0 and 1
12

Memory Unit
 Store programs and data
 Two classes of storage
 Primary storage
 Fast
 Programs must be stored in memory while they are being executed
 Large number of semiconductor storage cells
 Processed in words
 Address
 RAM and memory access time
 Memory hierarchy – cache, main memory
 Secondary storage – larger and cheaper
13

Arithmetic and Logic Unit
(ALU)
 Most computer operations are executed in
ALU of the processor.
 – Load the operands into memory
 – bring them to the processor
 – perform operation in ALU
 – store the result back to memory or retain in the
processor.
 Registers
 Fast control of ALU
14

Control Unit
 All computer operations are controlled by the control
unit.
 The timing signals that govern the I/O transfers are
also generated by the control unit.
 Control unit is usually distributed throughout the
machine instead of standing alone.
 Operations of a computer:
 Accept information in the form of programs and data through an
input unit and store it in the memory
 Fetch the information stored in the memory, under program control,
into an ALU, where the information is processed
 Output the processed information through an output unit
 Control all activities inside the machine through a control unit
15

The operations of a computer
 The computer accepts information in the form of
programs and data through an input unit and
stores it in the memory.
 Information stored in the memory is fetched
under program control into an arithmetic and
logic unit, where it is processed.
 Processed information leaves the computer
through an output unit.
 All activities in the computer are directed by the
control unit.
16

Review
 Activity in a computer is governed by instructions.
 To perform a task, an appropriate program
consisting of a list of instructions is stored in the
memory.
 Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
 Data to be used as operands are also stored in the
memory.
18

A Typical Instruction
 Add LOCA, R0
 Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and
added to the contents of R0 – the resulting sum is
stored in register R0.
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Separate Memory Access and
ALU Operation
 Load LOCA, R1
 Add R1, R0
 Whose contents will be overwritten?
20

Connection Between the
Processor and the Memory
21
Connections between the processor and the memory.
Processor
PC
IR
MDR
Control
ALU
R
n 1
-
R1
R0
MAR
n-general purpose
registers
Memory

Registers
 Instruction register (IR)
 Program counter (PC)
 General-purpose register (R0 – Rn-1)
 Memory address register (MAR)
 Memory data register (MDR)
22

Typical Operating Steps
 Programs reside in the memory through input
devices
 PC is set to point to the first instruction
 The contents of PC are transferred to MAR
 A Read signal is sent to the memory
 The first instruction is read out and loaded
into MDR
 The contents of MDR are transferred to IR
 Decode and execute the instruction
23

Typical Operating Steps
(Cont’)
 Get operands for ALU
 General-purpose register
 Memory (address to MAR – Read – MDR to ALU)
 Perform operation in ALU
 Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR – Write)
 During the execution, PC is
incremented to the next instruction
24

Interrupt
 Normal execution of programs may be preempted if
some device requires urgent servicing.
 The normal execution of the current program must
be interrupted – the device raises an interrupt
signal.
 Interrupt-service routine
 Current system information backup and restore (PC,
general-purpose registers, control information,
specific information)
25

Bus Structures
 There are many ways to connect different
parts inside a computer together.
 A group of lines that serves as a connecting
path for several devices is called a bus.
 Address/data/control
26

Bus Structure
 Single-bus
27
 Multiple Buses

Speed Issue
 Different devices have different
transfer/operate speed.
 If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be
very low.
 How to solve this?
 A common approach – use buffers.
e.g.- Printing the characters
28

Performance
 The most important measure of a computer is
how quickly it can execute programs.
 Three factors affect performance:
 Hardware design
 Instruction set
 Compiler
30

Performance
 Processor time to execute a program depends on the hardware
involved in the execution of individual machine instructions.
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Main
memory Processor
Bus
Cache
memory
Figure 1.5. The processor cache.

Performance
 The processor and a relatively small cache
memory can be fabricated on a single
integrated circuit chip.
 Speed
 Cost
 Memory management
32

Processor Clock
 Processor circuit is controlled by Clock.
 Clock defines regular time intervals called clock
cycle (P)
 To execute each instruction, processor divides
action into several steps (Basic Steps), each of
which completes in one clock cycle.
 Length of P affects processor performance
 Clock rate (R=1/P) cycles per second
 Hertz (Hz)– cycles per second
 Mega(M), Giga(G)
 500MHz-> 500 million cycles per second
 1.25GHz -> 1250 million cycles per second
( clock periods are 2 and 0.8 nanoseconds respectively)
33

Basic Performance Equation
 T – processor time required to execute a program that
has been prepared in high-level language
 N – number of actual machine language instructions
needed to complete the execution
 S – average number of basic steps needed to execute
one machine instruction. Each step completes in one
clock cycle
 R – clock rate- cycles per second
 Basic Performance Equation
 How to improve T? Reduce value of T
 Reduce N and S, Increase R, but these affect one
another 34
R
S
N
T



Basic Performance Equation
 Changing one may affect another.
 Introducing a new feature in design of processor will lead
to improved performance only if it reduces T.
 900MHz clock does not provide better performance than
700MHz because it may different S.
35

Clock Rate
 Increase clock rate(2-ways)
 Improve the integrated-circuit (IC) technology to make
the circuits faster
 Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps
needed)
 Increases in R that are entirely caused by
improvements in IC technology affect all
aspects of the processor’s operation equally
except the time to access the main memory.
36

Performance Measurement
 T is difficult to compute.
 Measure computer performance using benchmark programs.
 Synthetic programs do not properly predict the performance.
 System Performance Evaluation Corporation (SPEC) selects
and publishes representative application programs for
different application domains, together with test results for
many commercially available computers.
 Game Playing, compiler and database application, numerical
intensive astrophysics and quantum chemistry.
 Compile and run (no simulation)
 Reference computer
 SPEC95-> SUN SPARCStation 10/40
 SPEC2000-> UltraSPARC10 workstation 37

Performance Measurement
38




n
1
i
n
1
i )
SPEC
(
rating
SPEC
Overall
under test
computer
on the
time
Running
computer
reference
on the
time
Running
rating
SPEC
• SPEC rating of 50 means computer under test is 50 time
faster than UltraSPARC10 workstation.
•Test is repeated for all program in SPEC suite and
geometric mean is computed.

Machine
Instructions and
Programs
39

40
Objectives
 Machine instructions and program execution,
including branching and subroutine call and return
operations.
 Addressing methods for accessing register and
memory operands.
 Assembly language for representing machine
instructions, data, and programs.
 Program-controlled Input/Output operations.

Memory Locations,
Addresses, and
Operations
41

42
Memory Location, Addresses,
and Operation
 Operands and
instructions are
stored in memory
 Memory consists of
many millions of
storage cells, each of
which can store 1 bit.
 Word of information.
 Data is usually
accessed in n-bit
groups. n is called
word length.
 Word length 16 to 64
bits.
second word
first word
Fig: Memory words.
n bits
last word
i th word
•
•
•
•
•
•

43
and Operation
 32-bit word length example
(b) Four characters
character
character
character character
(a) A signed integer
Sign bit: for positive numbers
for negative numbers
ASCII
ASCII
ASCII
ASCII
32 bits
8 bits 8 bits 8 bits 8 bits
b31 b30 b1 b0
b31 0
=
b31 1
=
•
•
•

44
and Operation
 To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location
are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240

45
and Operation
 It is impractical to assign distinct addresses
to individual bit locations in the memory.
 The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory – byte-
addressable memory.
 Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,… with each
word consisting of 4 bytes.

46
Big-Endian and Little-Endian Assignments
2
k
4
- 2
k
3
- 2
k
2
- 2
k
1
- 2
k
4
-
2
k
4
-
0 1 2 3
4 5 6 7
0
0
4
2
k
1
- 2
k
2
- 2
k
3
- 2
k
4
-
3 2 1 0
7 6 5 4
Byte address
Byte address
(a) Big-endian assignment (b) Little-endian assignment
4
Word
address
•
•
•
•
•
•
Big-Endian: lower byte addresses are used for the most
significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used
for the less significant bytes of the word
Word
address
8 bits 8 bits 8 bits 8 bits

47
Big-Endian: MSB Byte will store first. MSB Byte will store at the
lowest memory address
Little-Endian: LSB byte will store first. So the LSB Byte will
store at the lowest memory address
Big-endian Little-endian

48
Big-Endian: MSB Byte will store first. MSB Byte will store at the
lowest memory address
Little-Endian: LSB byte will store first. So the LSB Byte will
store at the lowest memory address
On big-endian (PowerPC, SPARC, and Internet), the 32-bit value
x01234567 is stored as four bytes 0x01, 0x23, 0x45, 0x67, while
on little-endian (Intel x86), it will be stored in reverse order:

49
and Operation
 Bits, Byte, Word
 Address ordering of bytes
 Word alignment
 Words locations have aligned addresses in memory
if they begin at a byte address. that is a multiple of
the number of bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….
 32-bit word: word addresses: 0, 4, 8,….
 64-bit word: word addresses: 0, 8,16,….
 Access number(1 word), character(1 Byte), and
character string(multiple bytes)

50
Memory Operation
 Load (or Read or Fetch) Memory  Processor
 Copy the content. The memory content doesn’t change.
 Processor specifies address
 Registers can be used to store read data
 Store (or Write) Processor  Memory
 Overwrite the content in memory
 Processor specifies address and Data – Store
 Registers can be used ( 1 word)
 When byte is transferred -> located in low order(rightmost)
byte position of the register

51
Instruction and
Instruction
Sequencing

52
“Must-Perform” Operations
 Data transfers between the memory and the
processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers

53
Register Transfer Notation
 Identify a location by a symbolic name standing for its
hardware binary address (LOC, PLACE,R0,R1,
DATAIN,DATAOUT…)
 Contents of a location are denoted by placing square
brackets around the name of the location (R1←[LOC],
R3 ←[R1]+[R2])
 Register Transfer Notation (RTN)
RHS : denotes value
LHS : name of location where value is placed, overwriting old
content of location.

54
Assembly Language Notation
 Represent machine instructions and
programs.
 Move LOC, R1 => R1←[LOC]
 Add R1, R2, R3 => R3 ←[R1]+[R2]

55
CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite
often
 General Register
 Registers hold operands thus reduce memory
traffic
 Register bookkeeping
 Stack
 Operands and result are always in the stack

56
Instruction Formats
 C=A+B
 Three-Address Instructions
 ADD A,B,C C ← [A] + [B]
 ADD R2, R3, R1 R1 ← [R2] + [R3]
 Two-Address Instructions
 ADD A,B B ← [A] + [B]
 Move B,C C← [B]
 ADD R2, R1 R1 ← [R1] + [R2]
 One-Address Instructions
 ADD M AC ← [AC] + [M]
 Load A AC ← [A]
 Store A A ← [AC]
 Load A, ADD B, Store C
 Zero-Address Instructions
 ADD TOS ← [TOS] + [TOS – 1]

57
Instruction Formats
 Move Source, Destination
Move A ,Ri == Load A ,Ri
Move Ri ,A == Store Ri , A
 Arithmetic operation allowed only on
processor register C=A+B
 Same, one operand in memory and other in
register

58
Instruction Formats
Example: Evaluate (A+B)  (C+D)
 Three-Address
1. ADD A, B, R1 ; R1 ← [A] + [B]
2. ADD C, D, R2 ; R2 ← [C] + [D]
3. MUL R1, R2, X ; X ← [R1]  [R2]

59
Instruction Formats
 Two-Address
1. MOV A, R1 ; R1 ← [A]
2. ADD B, R1 ; R1 ← [R1] + [B]
3. MOV C, R2 ; R2 ← [C]
4. ADD D, R2 ; R2 ← [R2] + [D]
5. MUL R2, R1 ; R1 ← [R1]  [R2]
6. MOV R1, X ; X← [R1]

60
Instruction Formats
 One-Address
1. LOAD A ; AC ← [A]
2. ADD B ; AC ← [AC] + [B]
3. STORE T ; T ← [AC]
4. LOAD C ; AC ← [C]
5. ADD D ; AC ← [AC] + [D]
6. MUL T ; AC ← [AC]  [T]
7. STORE X ; X ← [AC]

61
Instruction Formats
 Zero-Address
1. PUSH A ; TOS ← [A]
2. PUSH B ; TOS ← [B]
3. ADD ; TOS ← [A + B]
4. PUSH C ; TOS ← [C]
5. PUSH D ; TOS ← [D]
6. ADD ; TOS ← [C + D]
7. MUL ; TOS ← [C+D][A+B]
8. POP X ; X ← [TOS]

62
Using Registers
 Registers are faster
 Shorter instructions
 The number of registers is smaller (e.g. 32
registers need 5 bits)
 Potential speedup
 Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.

63
Instruction Execution and
Straight-Line Sequencing
R0,C
B,R0
A,R0
Move
i + 8
Begin execution here Move
i
Contents
Address
C
B
A
the program
Data for
segment
program
3-instruction
Add
i + 4
Figure 2.8. A program for C  [A] + [B].
Assumptions:
- One memory operand
per instruction
- 32-bit word length
- Memory is byte
addressable
- Full memory address
can be directly specified
in a single-word instruction
Two-phase procedure
-Instruction fetch
-Instruction execute
PC=i

64
Branching
NUMn
NUM2
NUM1
R0,SUM
NUMn,R0
NUM3,R0
NUM2,R0
NUM1,R0
Figure 2.9. A straight-line program for adding n numbers.
Add
Add
Move
SUM
i
Move
Add
i 4n
+
i 4n 4
-
+
i 8
+
i 4
+
•
•
•
•
•
•
•
•
•

65
Branching
N,R1
Move
NUMn
NUM2
NUM1
R0,SUM
R1
"Next" number to R0
Figure 2.10. Using a loop to add n numbers.
LOOP
Decrement
Move
LOOP
loop
Program
Determine address of
"Next" number and add
N
SUM
n
R0
Clear
Branch>0
•
•
•
•
•
•
 Branch target
 Conditional branch
 Branch >0 Loop
if the result of immediately
receding instruction is > 0.

66
Condition Codes
 Processor keeps track of information about
results of various operations for use by
subsequent conditional branch instructions
 Condition code flags (bits)
 Condition code register / status register
 N (negative) set to 1 if result is negative, otherwise cleared to 0
 Z (zero) set to 1 if result is 0, otherwise cleared to 0
 V (overflow) set to 1 if arithmetic overflow occurs, otherwise 0
 C (carry) set to 1 if carry-out results from operation, otherwise 0
 Different instructions affect different flags

67
Condition Codes
 N and Z affected by arithmetic and logic operation.
 N and Z are affected by Move,Load,Store.

68
Condition Codes
 N and Z affected by arithmetic and logic operation.
 N and Z are affected by Move,Load,Store.

70
Generating Memory Addresses
 How to specify the address of branch target?
 Can we give the memory operand address
directly in a single Add instruction in the loop?
 Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.

71
Addressing Modes
The different ways in
which the location of
an operand is
specified in an
instruction are
referred to as
addressing modes.
Name Assem bler syntax Addressing Function
Immediate #Value Operand = Value
Register Ri EA = Ri
Absolute(Direct) LOC EA = LOC
Indirect (Ri ) EA = [Ri ]
(LOC) EA = [LOC]
Index X(Ri) EA = [Ri ] + X
Basewith index (Ri ,Rj ) EA = [Ri ] + [Rj ]
Basewith index X(Ri,Rj ) EA = [Ri ] + [Rj ] + X
and offset
Relative X(PC) EA = [PC] + X
Autoincrement (Ri )+ EA = [Ri ] ;
Increment Ri
Autodecrement (Ri ) Decrement Ri ;
EA = [Ri]


Effective Address (EA)
 In the addressing modes, the instruction does
not give the operand or its address explicitly.
Instead, it provides information from which an
effective address (EA) can be derived by the
processor when the instruction is executed.
 The effective address is then used to access
the operand.
72

73
Addressing Modes
 Immediate
 The use of a constant in put value 5 in R1
MOV #5, R1 i.e. R1 ← 5
MOV #NUM1, R2 ; to copy the variable memory address
 Register
 Indicate which register holds the operand, name of the register is
given
 Direct (Absolute) Address
 Use the given address to access a memory location
 E.g. Move NUM1, R1
Move R0, SUM
Opcode Mode ...
0x1000
NUM1
0x1000
R2

74
Indirect Addressing
 Indirect Addressing
 Indirection and Pointer
 Indirect addressing through a general purpose register.
 EA of operand is the contents of register or memory
location whose address specified in instruction
ADD (R1), R0
.
.
.
B Operand
R1 B
 Indicate the register (e.g. R1) that
holds the address of the variable
(e.g. B) that holds the operand
ADD (R1), R0
 The register or memory location
that contain the address of an
operand is called a pointer

75
Addressing Modes
Indirect Addressing
 Indirect Addressing
 Indirect addressing through a memory addressing.
ADD (A), R0
.
.
.
B Operand
A B
 Indicate the memory variable
(e.g. A )that holds the address
of the variable (e.g. B) that
holds the operand
ADD (A), R0

Indirect Addressing
Example
 Addition of N numbers
1. Move N,R1 ; N = Numbers to add
2. Move #NUM,R2 ; R2= Address of 1st no.
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = [NUM1] + [R0]
5. Add #4, R2 ; R2= To point to the next
; number
6. Decrement R1 ; R1 = [R1] -1
7. Branch>0 Loop ; Check if R1>0 or not if
; yes go to Loop
8. Move R0, SUM ; SUM= Sum of all no.
76

Example
1. Move N,R1 ; N = 5
2. Move #NUM,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 10 + 00 = 10
5. Add #4, R2 ; R2 = 10004H
6. Decrement R1 ; R1 = 4
7. Branch>0 Loop ; Check if R1>0 if
; yes go to Loop
8. Move R0, SUM ; SUM=
77
10000H 10004H 10008H 1000CH 10010H
10 20 30 40 50
NUM

Example
1. Move N,R1 ; N = 5
2. Move #NUM,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 20 + 10 = 30
5. Add #4, R2 ; R2 = 10008H
; yes go to Loop
78
10000H 10004H 10008H 1000CH 10010H
10 20 30 40 50
NUM

Example
1. Move N,R1 ; N = 5
2. Move #NUM,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 30 + 30 = 60
5. Add #4, R2 ; R2 = 1000CH
; yes go to Loop
79
10000H 10004H 10008H 1000CH 10010H
10 20 30 40 50
NUM

Example
1. Move N,R1 ; N = 5
2. Move #NUM,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 40 + 60 = 100
5. Add #4, R2 ; R2 = 10010H
; yes go to Loop
80
10000H 10004H 10008H 1000CH 10010H
10 20 30 40 50
NUM

Example
1. Move N,R1 ; N = 5
2. Move #NUM,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 50 + 100 = 150
5. Add #4, R2 ; R2 = 10014H
; yes go to Loop
8. Move R0, SUM ; SUM =
81
10000H 10004H 10008H 1000CH 10010H
10 20 30 40 50
NUM

Example
1. Move N,R1 ; N = 5
2. Move #NUM,R2 ; R2= 10000H
3. Clear R0 ; R0 = 00
4. Loop : Add (R2), R0 ; R0 = 50 + 100 = 150
5. Add #4, R2 ; R2 = 10014H
; yes go to Loop
8. Move R0, SUM ; SUM = 150
82
10000H 10004H 10008H 1000CH 10010H
10 20 30 40 50
NUM

Addressing Modes
Indexing and Arrays
 Indexing and Array
 The EA of the operand is generated by
adding a constant value to the contents of a
register.
 X(Ri) ; EA= X + (Ri) X= Signed number
 X defined as offset or displacement
83

84
Addressing Modes
Indexing and Arrays
 In general, the Index mode facilitates access to an operand
whose location is defined relative to a reference point within
the data structure in which the operand appears.
 Index Addressing Mode
X(Ri) so EA= X+[Ri]
 2D Array (Base with Index AM)
 (Ri, Rj) so EA = [Ri] + [Rj]
 Rj is called the base register
 3D Array (Base with Index and offset AM)
 X(Ri, Rj) so EA = X + [Ri] + [Rj]

Addressing Modes
Indexing and Arrays
Address Memory
Add 20(R1), R2
.
.
.
.
10000H
Offset=20
.
.
.
.
10020H Operand
R1 10000H
85
R1 20H
Address Memory
Add 10000H(R1), R2
.
.
.
.
10000H
Offset=20
.
.
.
.
10020H Operand
Offset is given as a Constant Offset is in the index register

Addressing Modes
Indexing and Arrays
86
Task: To compute sum of all
scores obtained on each of
tests and store these sums in
memory locations
SUM1,SUM2,SUM3.

Addressing Modes
Indexing and Arrays
87

88
Addressing Modes
Relative Addressing
 Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
 X(PC) – note that X is a signed number
 Branch>0 LOOP
 This location is computed by specifying it as an
offset from the current value of PC.
 Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.

100
101
102
103
104
0
1
2
89
Addressing Modes
Relative Addressing
 Relative Address
 EA = PC + Relative Addr (X)
X = 100
1 1 0 A
PC = 2
+
Could be Positive or
Negative
(2’s Complement)

90
Addressing Modes
Additional Modes
 Autoincrement mode – the effective address of the operand is the
contents of a register specified in the instruction. After accessing the
operand, the contents of this register are automatically incremented to
point to the next item in a list.
 (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit operands,
and 4 for 32-bit operands.
 Autodecrement mode: -(Ri) – decrement first
R0
Clear
R0,SUM
R1
(R2)+,R0
Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
Initialization
Move
LOOP Add
Decrement
LOOP
#NUM1,R2
N,R1
Move
Move
Branch>0

Assembly Language
 Machine instructions are represented by patterns of 0s and 1s.
So these patterns represented by symbolic names called
“mnemonics”
 E.g. Load, Store, Add, Move, BR, BGTZ
 A complete set of such symbolic names and rules for their use
constitutes a programming language, referred to as an assembly
language.
 The set of rules for using the mnemonics and for specification of
complete instructions and programs is called the syntax of the
language.
 Programs written in an assembly language can be automatically
translated into a sequence of machine instructions by a program
called an assembler.
 The assembler program is one of a collection of utility programs
that are a part of the system software of a computer.
92

Assembly Language
 The user program in its original alphanumeric text format
is called a source program, and the assembled machine-
language program is called an object program.
 The assembly language for a given computer is not case
sensitive.
 E.g. MOVE R1, SUM
93
Opcode Operand(s) or Address(es)

Assembler Directives
 In addition to providing a mechanism for representing
instructions in a program, assembly language allows the
programmer to specify other information needed to
translate the source program into the object program.
 Assign numerical values to any names used in a program.
 For e,g, name TWENTY is used to represent the value 20. This
fact may be conveyed to the assembler program through an
equate statement such as TWENTY EQU 20
 If the assembler is to produce an object program according
to this arrangement, it has to know
 How to interpret the names
 Where to place the instructions in the memory
 Where to place the data operands in the memory
94

Assembly language representation for the
program
 Label: Operation Operand(s) Comment
95

Assembly and Execution of
Programs
 A source program written in an assembly language must be
assembled into a machine language object program before it can
be executed. This is done by the assembler program, which
replaces all symbols denoting operations and addressing modes
with the binary codes used in machine instructions, and replaces
all names and labels with their actual values.
 A key part of the assembly process is determining the values that
replace the names. Assembler keep track of Symbolic name and
Label name, create table called symbol table.
 The symbol table created by scan the source program twice.
 A branch instruction is usually implemented in machine code by
specifying the branch target as the distance (in bytes) from the
present address in the Program Counter to the target instruction.
The assembler computes this branch offset, which can be positive
or negative, and puts it into the machine instruction.
96

Assembly and Execution of
Programs
 The assembler stores the object program on the secondary storage device
available in the computer, usually a magnetic disk. The object program must be
loaded into the main memory before it is executed. For this to happen, another
utility program called a loader must already be in the memory.
 The loader must know the length of the program and the address in the memory
where it will be stored.
 The assembler usually places this information in a header preceding the object
code (Like start/end offset address).
 When the object program begins executing, it proceeds to completion unless there
are logical errors in the program. The user must be able to find errors easily.
 The assembler can only detect and report syntax errors. To help the user find
other programming errors, the system software usually includes a debugger
program.
 This program enables the user to stop execution of the object program at some
points of interest and to examine the contents of various processor registers and
memory locations.
97

Number Notation
 Decimal Number
 ADD #93,R1
 Binary Number
 ADD #%0101110,R1
 Hexadecimal Number
 ADD #$5D,R1
98

99
Types of Instructions
 Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data value is
not modified

100
Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1

101
Data Manipulation Instructions
 Arithmetic
 Logical & Bit Manipulation
 Shift
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Negate NEG
Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Complement carry COMC
Enable interrupt EI
Disable interrupt DI
Name Mnemonic
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry RORC
Rotate left through carry ROLC

102
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare
(Subtract)
CMP
Test (AND) TST
Subtract A – B but
don’t store the result
1 0 1 1 0 0 0 1
0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0
Mask

103
Conditional Branch
Instructions
Mnemonic Branch Condition Tested Condition
BZ Branch if zero Z = 1
BNZ Branch if not zero Z = 0
BC Branch if carry C = 1
BNC Branch if no carry C = 0
BP Branch if plus S = 0
BM Branch if minus S = 1
BV Branch if overflow V = 1
BNV Branch if no overflow V = 0

104
Basic Input/Output
Operations

105
I/O
 The data on which the instructions operate
are not necessarily already stored in memory.
 Data need to be transferred between
processor and outside world (disk, keyboard,
etc.)
 I/O operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.

106
Program-Controlled I/O
Example
 Read in character input from a keyboard and
produce character output on a display screen.
 Rate of data transfer (keyboard, display, processor)
 Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
 A solution: on output, the processor sends the first
character and then waits for a signal from the display
that the character has been received. It then sends the
second character. Input is sent from the keyboard in a
similar way.

107
Example
- Registers
- Flags
- Device interface
DATAIN DATAOUT
SIN SOUT
Keyboard Display
Bus
.
Processor
-DATAIN & DATAOUT Buffer register hold 1 Character
-Initial value of SIN=0 and SOUT=1
-When key is pressed SIN=1 and character in DATAIN
-Once data is transferred to processor SIN=0
-When want to print a character in DATAOUT
-When SOUT=1 display is ready to display
-When displaying ,SOUT=0 after display SOUT=1

108
Example
 Machine instructions that can check the state
of the status flags and transfer data:
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1
WRITEWAIT Branch to WRITEWAIT if SOUT = 0
Output from R1 to DATAOUT

109
Example
 Memory-Mapped I/O – some memory address
values are used to refer to peripheral device buffer
registers. No special instructions are needed. Also
use device status registers.
 E.g. Movebyte DATAIN,R1
 Movebyte R1,DTATOUT
 READWAIT Testbit #3, INSTATUS
Branch=0 READWAIT
MoveByte DATAIN, R1
 WRITEWAIT Testbit #3, OUTSTATUS
Branch=0 WRITEWAIT
MoveByte R1, DATAOUT

110
Example

112
Stacks
 A stack is a list of data elements, usually words, with the
accessing restriction that elements can be added or removed at
one end of the list only. This end is called the top of the stack,
and the other end is called the bottom. The structure is
sometimes referred to as a pushdown stack.
 last-in–first-out (LIFO) stack working.
 The terms push and pop are used to describe placing a new
item on the stack and removing the top item from the stack,
respectively.
 The stack pointer, SP, is used to keep track of the address of
the element of the stack that is at the top at any given time.

116
• Stack has fixed space in memory
• We should avoid pushing item on stack, if stack has
reached its maximum size.
• Bottom is 0x2000, upto 0x1500, Initial value is 0x2004
• We should avoid popping item from empty stack

Queue
 FIFO basis
 Data are stored in and retrieved from a queue
on a first-in–first-out (FIFO) basis. Thus, if we
assume that the queue grows in the direction
of increasing addresses in the memory, new
data are added at the back (high-address
end) and retrieved from the front (low-
address end) of the queue.
118

Differences between a stack
and a queue
 Stack
 LIFO
 One end is fixed other
end for PUSH and
POP item
 One pointer used
 Fixed Size
 Queue
 FIFO
 One end is to add
item and other is to
remove item
 Two Pointer is used
 Not fixed size
119

Subroutines
 In a given program, it is often necessary to perform a particular
task many times on different data values. Such a block of
instructions is usually called a subroutine.
 However, to save space, only one copy of this block is placed in
the memory, and any program that requires the use of the
subroutine simply branches to its starting location.
 When a program branches to a subroutine we say that it is
calling the subroutine. The instruction that performs this branch
operation is named a Call instruction.
 After a subroutine has been executed, the calling program must
resume execution, continuing immediately after the instruction
that called the subroutine. The subroutine is said to return to the
program that called it, and it does so by executing a Return
instruction.
121

Subroutines
 Since the subroutine may be called from different places in a
calling program, provision must be made for returning to the
appropriate location. The location where the calling program
resumes execution is the location pointed to by the updated
program counter (PC) while the Call instruction is being executed.
 Hence, the contents of the PC must be saved by the Call
instruction to enable correct return to the calling program.
 The way in which a computer makes it possible to call and return
from subroutines is referred to as its subroutine linkage method.
 The simplest subroutine linkage method is to save the return
address in a specific location, which may be a register dedicated to
this function. Such a register is called the link register.
 When the subroutine completes its task, the Return instruction
returns to the calling program by branching indirectly through the
link register.
122

Subroutines
 The Call instruction is just a special branch
instruction that performs the following
operations:
 Store the contents of the PC in the link register
 Branch to the target address specified by the Call
instruction
 The Return instruction is a special branch
instruction that performs the following operation
 Branch to the address contained in the link register
123

Subroutine Nesting and the
Processor Stack
 A common programming practice, called subroutine
nesting, is to have one subroutine call another.

 In this case, the return address of the second call is
also stored in the link register, overwriting its
previous contents. Hence, it is essential to save the
contents of the link register in some other location
before calling another subroutine. Otherwise, the
return address of the first subroutine will be lost.
 That is, return addresses are generated and used in
a last-in–first-out order. This suggests that the return
addresses associated with subroutine calls should
be pushed onto the processor stack. 125

Parameter Passing
 When calling a subroutine, a program must provide to the
subroutine the parameters  the operands or their
addresses, to be used in the computation.
 Later, the subroutine returns other parameters, which are
the results of the computation.
 This exchange of information between a calling program
and a subroutine is referred to as parameter passing.
 Parameter passing may be accomplished in several ways.
The parameters may be placed in registers, in memory
locations, or on the processor stack where they can be
accessed by the subroutine.
126

Program with subroutine
Parameters passed through registers.
 Calling Program
1. Move N, R1
2. Move #NUM1,R2
3. Call LISTADD
4. Move R0,SUM
 Subroutine
1. LISTADD: Clear R0
2. LOOP: Add (R2)+,R0
3. Decrement R1
4. Branch>0 LOOP
5. Return
127

Parameter Passing by Value and
by Reference
 Instead of passing the actual Value(s), the
calling program passes the address of the
Value(s). This technique is called passing by
reference.
 The second parameter is passed by value,
the actual number of entries, is passed to the
subroutine.
128

Program with subroutine
Parameters passed on the stack.
 MoveMultiple R0-R2, -(SP)
 MoveMultiple to store contents of register R0
through R2 on the stack
129

Parameters passed on the stack.
130

The Stack Frame
 If the subroutine requires more space for local memory
variables, the space for these variables can also be
allocated on the stack  this area of stack is called
Stack Frame.
 For e.g. during execution of the subroutine, six locations
at the top of the stack contain entries that are needed by
the subroutine.
 These locations constitute a private work space for the
subroutine, allocated at the time the subroutine is
entered and deallocated when the subroutine returns
control to the calling program.
131

The Stack Frame
 Frame pointer (FP), for convenient
access to the parameters passed
to the subroutine and to the local
memory variables used by the
subroutine.
 In the figure, we assume that four
parameters are passed to the
subroutine, three local variables
are used within the subroutine,
and registers R2, R3, and R4
need to be saved because they
will also be used within the
subroutine.
 Parameter can be accessed as
8(FP),12(FP) and local variables
can be accessed as -4(FP),
-12(FP).
 When nested subroutines are
used, the stack frame of the
calling subroutine would also
include the return address, as we
will see in the example that
follows.
132

133
Stack Frames for Nested Subroutines

Stack Frames for Nested Subroutines
134

136
Logical
• Not dst
complements all bits contained in operand dst.
• Negate R0
converts content of R0 to its negative value.
• And Src, Dst
performs bitwise AND operation between contents of Src and
Dst
• Ex: Suppose 4 ASCII characters are stored in 32-bit R0 and
want to check whether leftmost character is Z(010110010)
And #$FF000000, R0 ; clear rightmost 3 characters
Compare #$5A000000, R0 ; Compares R0 with Z
Branch=0 YES

137
Logical Shifts
 Logical shift – shifting left (LShiftL)
LShiftL count,dst
 Left shifts the content of Dst by position specified by count
 At right hand side vacated positions are filled with zeros
 At left hand side bits shifted out through carry flag C
 Involving carry, useful in handling arithmetic operation that
have operands of size > 1 word.

138
Logical Shifts
 Logical shift –shifting right (LShiftR)

139
Subroutine to pack 2 BCD digits
• Suppose 2 decimal digits represented in ASCII code are
located in memory at byte locations LOC, LOC+1
• Task: To represent each digit in 4-bit BCD code and store
them in single byte location PACKED(Packed BCD format).
• Appendix E shows rightmost 4 bits of ASCII code for a
decimal digit corresponds to BCD code for that digit.
•Operation : Extract lower order 4 bits in LOC and LOC+1
and concatenate them in single byte at PACKED.

141
Arithmetic Shifts
• Shifting number to left by bit = multiplying number by 2
• Shifting number to right by bit = dividing number by 2
• Overflow might occur on shifting left
• Reminder might be lost on shifting right
• On right shift, sign bit must be repeated as fill in bit for
vacated position.
• Arithmetic shift left is same as logical shift left.

142
Rotate
• In shift operation, every bit is shifted out, except the
last one which is retained in Carry flag bit
• To preserve all bit, rotate instruction is used, which
move the bits that are shifted out of one end operand
back into the other end.

144
Multiplication and Division
 Multiply Ri, Rj
Rj ← [Ri] х [Rj]
 2n-bit product case: high-order half in R(j+1)
 Divide Ri, Rj
Rj ← [Ri] / [Rj]
 Quotient  Rj,
 Remainder R(j+1)

145
Encoding of
Machine
Instructions

146
Encoding of Machine
Instructions
 Assembly language program needs to be converted into
machine instructions. (ADD = 0100 in ARM instruction set)
 In the previous section, an assumption was made that all
instructions are one word in length.
 OP code: the type of operation to be performed and the type
of operands used may be specified using an encoded binary
pattern
 Suppose 32-bit word length, 8-bit OP code (how many
instructions can we have?), 16 registers in total (how many
bits?), 3-bit addressing mode indicator.
 Add R1, R2
 Move 24(R0), R5
 LshiftR #2, R0
 Move #$3A, R1
OP code Source Dest Other info
8 7 7 10
(a) One-word instruction

147
Encoding of Machine
Instructions
 What happens if we want to specify a memory
operand using the Absolute addressing mode?
 Move R2, LOC
 14-bit for LOC – insufficient
 Solution – use two words
(b) Two-word instruction
Memory address/Immediate operand
OP code Source Dest Other info

148
Encoding of Machine
Instructions
 Then what if an instruction in which two operands
can be specified using the Absolute addressing
mode?
 Move LOC1, LOC2
 Solution – use two additional words
 This approach results in instructions of variable
length. Complex instructions can be implemented,
closely resembling operations in high-level
programming languages – Complex Instruction Set
Computer (CISC)

149
Encoding of Machine
Instructions
 If we insist that all instructions must fit into a single
32-bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
 It is still possible to define a highly functional
instruction set, which makes extensive use of the
processor registers.
 Add R1, R2 ----- yes
 Add LOC, R2 ----- no
 Add (R3), R2 ----- yes

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