Basic concepts in Verilog HDL

Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56
Basic Concepts
Mr. Anand H. D.
1
Basic Concepts
Department of Electronics & Communication Engineering
Dr. Ambedkar Institute of Technology
Bengaluru-56

Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 2
Topics to be covered
Lexical conventions
Data types
System tasks and Compiler directives
Basic Concepts

Let us discuss about
Lexical conventions
Data types
Basic Concepts

Basic Concepts
Lexical conventions
Multiple-line comments cannot be nested. However, one-line comments can be
embedded in multiple-line comments.
1. Whitespace
Blank spaces (b) , tabs (t) and newlines (n) comprise the whitespace. Whitespace is
ignored by Verilog except when it separates tokens. Whitespace is not ignored in strings.
2. Comments
Comments can be inserted in the code for readability and documentation.
There are two ways to write comments.
A one-line comment starts with "//". Verilog skips from that point to the end of line.
A multiple-line comment starts with "/*" and ends with "*/".
Examples:
a = b && c; // This is a one-line comment
/* This is a multiple line comment */
/* This is /* an illegal */ comment */
/* This is //a legal comment */

Basic Concepts
Lexical conventions
3. Operators
Operators are of three types: unary, binary, and ternary.
Unary operators precede the operand.
Binary operators appear between two operands.
Ternary operators have two separate operators that separate three operands.
Examples: a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands
4. Number Specification
There are two types of number specification in Verilog: sized and unsized.
A.)Sized numbers
B.) Unsized numbers
C.) X or Z values
D.) Negative numbers
E.)Underscore characters and question marks

Basic Concepts
Lexical conventions
A.)Sized numbers
Sized numbers are represented as <size> '<base format> <number>.
<size> is written only in decimal and specifies the number of bits in the number.
Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or
'B) and octal ('o or 'O).
The number is specified as consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a,
b, c, d, e, f.
Only a subset of these digits is legal for a particular base.
Uppercase letters are legal for number specification.
Examples:
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.

Basic Concepts
Lexical conventions
B.) Unsized numbers
Numbers that are specified without a <base format> specification are decimal
numbers by default.
Numbers that are written without a <size> specification have a default number
of bits that is simulator- and machine-specific (must be at least 32).
Examples: 23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number
C.) X or Z values
Verilog has two symbols for unknown and high impedance values.
These values are very important for modeling real circuits.
An unknown value is denoted by an x.
A high impedance value is denoted by z.

Basic Concepts
Lexical conventions
Examples:
12'h13x // This is a 12-bit hex number; 4 least significant bits unknown
6'hx // This is a 6-bit hex number
32‘dz // This is a 32-bit high impedance number
An x or z sets four bits for a number in the hexadecimal base, three bits for a
number in the octal base, and one bit for a number in the binary base.
If the most significant bit of a number is 0, x, or z, the number is automatically
extended to fill the most significant bits, respectively, with 0, x, or z. This makes it
easy to assign x or z to whole vector.
If the most significant digit is 1, then it is also zero extended.

Basic Concepts
Lexical conventions
D.) Negative numbers
Negative numbers can be specified by putting a minus sign before the size for a
constant number.
Size constants are always positive. It is illegal to have a minus sign between
<base format> and <number>.
An optional signed specifier can be added for signed arithmetic.
Examples:
-6'd3 // 8-bit negative number stored as 2's complement of 3
-6'sd3 // Used for performing signed integer math
4'd-2 // Illegal specification also zero extended.

Basic Concepts
Lexical conventions
E.)Underscore characters and question marks
An underscore character "_" is allowed anywhere in a number except the first
character.
Underscore characters are allowed only to improve readability of numbers and
are ignored by Verilog.
A question mark "?" is the Verilog HDL alternative for z in the context of numbers.
The ? is used to enhance readability in the casex and casez statements, where the
high impedance value is a don't care condition.
Examples:
12'b1111_0000_1010 // Use of underline characters for readability
4'b10?? // Equivalent of a 4'b10zz

Basic Concepts
Lexical conventions
5. Strings
A string is a sequence of characters that are enclosed by double quotes.
The restriction on a string is that it must be contained on a single line, that is, without a
carriage return. It cannot be on multiple lines.
Strings are treated as a sequence of one-byte ASCII values.
Examples: "Hello Verilog World" // is a string
"a / b" // is a string
6. Identifiers and Keywords
Keywords are special identifiers reserved to define the language constructs.
Keywords are in lowercase.
Identifiers are names given to objects so that they can be referenced in the design.
Identifiers are made up of alphanumeric characters, the underscore ( _ ), or the dollar sign ($).
Identifiers are case sensitive.
Identifiers start with an alphabetic character or an underscore. They cannot start with a digit
or a $ sign Examples: reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier

Basic Concepts
Lexical conventions
7. Escaped Identifiers
Escaped identifiers begin with the backslash ( ) character and end with
whitespace (space, tab, or newline).
All characters between backslash and whitespace are processed literally.
Any printable ASCII character can be included in escaped identifiers.
Neither the backslash nor the terminating whitespace is considered to be a part
of the identifier.
a+b-c
**my_name**

Lexical conventions
Data types
Basic Concepts

Basic Concepts
Data types
1. Value Set: Verilog supports four values and eight
strengths to model the functionality of real hardware
Value
Level
Condition in Hardware
Circuits
0 Logic zero, false condition
1 Logic one, true condition
x Unknown logic value
z
High impedance, floating
state
In addition to logic values, strength levels are often used to
resolve conflicts between drivers of different strengths in digital
circuits. Value levels 0 and 1 can have the strength levels listed
in table:
If two signals of unequal strengths are driven on a wire, the
stronger signal prevails. For example, if two signals of strength
strong1 and weak0 contend, the result is resolved as a strong1.
If two signals of equal strengths are driven on a wire, the
result is unknown. If two signals of strength strong1 and
strong0 conflict, the result is an x.
Strength levels are particularly useful for accurate modeling of
signal contention, MOS devices, dynamic MOS, and other low-
level devices.
Only trireg nets can have storage strengths large, medium, and
small.

Basic Concepts
Data types
2. Nets: Nets represent connections between hardware elements.
In the figure net a is connected to the output of and gate g1.
Net a will continuously assume the value computed at the output of
gate g1, which is b & c.
Nets are declared primarily with the keyword wire.
Nets are one-bit values by default unless they are declared explicitly as vectors
The terms wire and net are often used interchangeably. The default value of a net is z
(except the trireg net, which defaults to x).
Nets get the output value of their drivers. If a net has no driver, it gets the value z.
wire a; // Declare net a for the above circuit
wire b,c; // Declare two wires b,c for the above circuit
wire d = 1'b0; // Net d is fixed to logic value 0 at declaration.
Note that net is not a keyword but represents a class of data types such as wire, wand, wor, tri,
triand, trior, trireg, etc. The wire declaration is used most frequently.

Basic Concepts
Data types
3 Register:
Registers represent data storage elements.
Registers retain value until another value is placed onto them.
In Verilog, the term register merely means a variable that can hold a value. Unlike a net, a
register does not need a driver.
Verilog registers do not need a clock as hardware registers do. Values of registers can be
changed anytime in a simulation by assigning a new value to the register.
Register data types are commonly declared by the keyword reg.
The default value for a reg data type is x.
Example-1 Example of Register
reg reset; // declare a variable reset that can hold its value
initial // this construct will be discussed later
begin reset = 1'b1; //initialize reset to 1 to reset the digital circuit.
#100 reset = 1'b0; // after 100 time units reset is deasserted
end

Basic Concepts
Data types
Registers can also be declared as signed variables. Such registers can be used for signed
arithmetic.
Example-2 Signed Register Declaration
reg signed [63:0] m; // 64 bit signed value
integer i; // 32 bit signed value
4 Vectors
Nets or reg data types can be declared as vectors (multiple bit widths).
If bit width is not specified, the default is scalar (1-bit).
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
reg clock; // scalar register, default
reg [0:40] virtual_addr; // Vector register, virtual address 41 bits wide
Vectors can be declared at [high# : low#] or [low# : high#], but the left number in the squared
brackets is always the most significant bit of the vector.

Basic Concepts
Data types
Vectors can be declared at [high# : low#] or [low# : high#], but the left number in the squared
brackets is always the most significant bit of the vector.
Vector Part Select
It is possible to address bits or parts of vectors.
busA[7] // bit # 7 of vector busA
bus[2:0] // Three least significant bits of vector bus,
virtual_addr[0:1] // Two most significant bits of vector virtual_addr
Variable Vector Part Select
Verilog HDl supports variable part selects of a vector. This allows part selects to be put in for loops
to select various parts of the vector.
There are two special part-select operators:
[<starting_bit>+:width] - part-select increments from starting bit
[<starting_bit>-:width] - part-select decrements from starting bit
The starting bit of the part select can be varied, but the width has to be constant.

Basic Concepts
Data types
The following example shows the use of variable vector part select:
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
//Using a variable part select, one can choose parts
byte = data1[31-:8]; //starting bit = 31, width =8 => data[31:24]
byte = data1[24+:8]; //starting bit = 24, width =8 => data[31:24]
byte = data2[31-:8]; //starting bit = 31, width =8 => data[24:31]
byte = data2[24+:8]; //starting bit = 24, width =8 => data[24:31]
255 …. …. 0
31 24
255 …. …. 0
31 24
0 …. …. 255
24 31
24 31 …. 255
0 ….
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

Basic Concepts
Data types
//The starting bit can also be a variable. The width has to be constant. Therefore, one can use
//the variable part select in a loop to select all bytes of the vector.
for (j=0; j<=31; j=j+1)
byte = data1[(j*8)+:8]; //Sequence is [7:0], [15:8]... [255:248]
255 ….. 2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
//Can initialize a part of the vector
data1[(byteNum*8)+:8] = 8'b0; //If byteNum = 1, clear 8 bits [15:8]
255 2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
*
*
*
*
*
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*
*
data1[(byteNum*5)-:10] = 10'b0; //If byteNum = 2
255 2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
*
*
*
*
*
*
*
*
*
*

Basic Concepts
Data types
5.Integer , Real, and Time Register Data Types:
Integer, real, and time register data types are supported in Verilog.
Integer: An integer is a general purpose register data type used for manipulating quantities.
Integers are declared by the keyword integer.
It is more convenient to declare an integer variable for purposes such as counting.
The default width for an integer is the host-machine word size, which is implementation-
specific but is at least 32 bits.
Registers declared as data type reg store values as unsigned quantities, whereas integers store
values as signed quantities.
Examples:
integer counter; // general purpose variable used as a counter.
Initial
counter = -1; // A negative one is stored in the counter

Basic Concepts
Data types
Real: Real number constants and real register data types are declared with the keyword real.
Real numbers cannot have a range declaration, and their default value is 0.
Example:
real delta; // Define a real variable called delta
initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer I
initial
i = delta; // i gets the value 2 (rounded value of 2.13)
They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which
is 3 x 106 ).
When a real value is assigned to an integer, the real number is rounded off to the
nearest integer.

Basic Concepts
Data types
Time: Verilog simulation is done with respect to simulation time. A special time register data type
is used in Verilog to store simulation time.
A time variable is declared with the keyword time. The width for time register data types is
implementation-specific but is at least 64 bits.
The system function $time is invoked to get the current simulation time.
Example:
time save_sim_time; // Define a time variable save_sim_time
Initial
save_sim_time = $time; // Save the current simulation time

Basic Concepts
Data types
Arrays: Arrays are allowed in Verilog for reg, integer, time, real, realtime and vector register data
types.
Multi-dimensional arrays can also be declared with any number of dimensions.
Arrays of nets can also be used to connect ports of generated instances.
Each element of the array can be used in the same fashion as a scalar or vector net.
Arrays are accessed by <array_name>[<subscript>]. For multi-dimensional arrays, indexes
need to be provided for each dimension.
Example:
integer count[0:7]; // An array of 8 count variables
reg bool[31:0]; // Array of 32 one-bit boolean register variables
time chk_point[1:100]; // Array of 100 time checkpoint variables
reg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id is 5 bits wide integer
matrix[4:0][0:255]; // Two dimensional array of integers
reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional array
wire [7:0] w_array2 [5:0]; // Declare an array of 8 bit vector wire
wire w_array1[7:0][5:0]; // Declare an array of single bit wires

Basic Concepts
Data types
It is important not to confuse arrays with net or register vectors.
A vector is a single element that is n-bits wide.
On the other hand, arrays are multiple elements that are 1-bit or n-bits wide
Examples of assignments to elements of arrays discussed above are shown below:
count[5] = 0; // Reset 5th element of array of count variables
chk_point[100] = 0; // Reset 100th time check point value
port_id[3] = 0; // Reset 3rd element (a 5-bit value) of port_id array.
matrix[1][0] = 33559; // Set value of element indexed by [1][0] to 33559
array_4d[0][0][0][0][15:0] = 0; //Clear bits 15:0 of the register accessed by indices [0][0][0][0]
port_id = 0; // Illegal syntax - Attempt to write the entire array
matrix [1] = 0; // Illegal syntax Attempt to write [1][0]..[1][255]

Basic Concepts
Data types
Memories: In digital simulation, one often needs to model register files, RAMs, and ROMs.
Memories are modeled in Verilog simply as a one-dimensional array of registers.
Each element of the array is known as an element or word and is addressed by a single array
index.
Each word can be one or more bits. It is important to differentiate between n 1-bit registers
and one n-bit register.
A particular word in memory is obtained by using the address as a memory array subscript.
Examples:
reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit words
reg [7:0] membyte[0:1023]; // Memory membyte with 1K 8-bit words(bytes)
membyte[511] // Fetches 1 byte word whose address is 511

Basic Concepts
Data types
Parameters
Verilog allows constants to be defined in a module by the keyword parameter.
Parameters cannot be used as variables. Parameter values for each module instance can be
overridden individually at compile time. This allows the module instances to be customized.
Parameter types and sizes can also be defined.
Examples:
parameter port_id = 5; // Defines a constant port_id
Parameter cache_line_width = 256; // Constant defines width of cache line
parameter signed [15:0] WIDTH; // Fixed sign and range for parameter WIDTH
Module definitions may be written in terms of parameters. Hardcoded numbers should be
avoided. Parameters values can be changed at module instantiation or by using the
defparam statement. Thus, the use of parameters makes the module definition flexible.

Basic Concepts
Data types
Module behavior can be altered simply by changing the value of a parameter.
Verilog HDL local parameters (defined using keyword localparam -) are identical to
parameters except that they cannot be directly modified with the defparam statement or by the
ordered or named parameter value assignment..
localparam state1 = 4'b0001,
state2 = 4'b0010,
state3 = 4'b0100,
state4 = 4'b1000;
The localparam keyword is used to define parameters when their values should not be
changed.
For example, the state encoding for a state machine can be defined using localparam. The
state encoding cannot be changed. This provides protection against inadvertent parameter
redefinition.

Basic Concepts
Data types
Strings
Strings can be stored in reg. The width of the register variables must be large enough to hold
the string.
Each character in the string takes up 8 bits (1 byte).
If the width of the register is greater than the size of the string, Verilog fills bits to the left of
the string with zeros.
If the register width is smaller than the string width, Verilog truncates the leftmost bits of the
string.
It is always safe to declare a string that is slightly wider than necessary.
reg [8*18:1] string_value; // Declare a variable that is 18 bytes wide
initial
string_value = "Hello Verilog World"; // String can be stored in variable

Basic Concepts
Data types
Special characters serve a special purpose in displaying strings, such as newline, tabs, and
displaying argument values.
Special characters can be displayed in strings only when they are preceded by escape
characters, as shown in Table.

Lexical conventions
Data types
Basic Concepts

Basic Concepts
Verilog provides standard system tasks for certain routine operations.
All system tasks appear in the form $<keyword>.
$display is the main system task for displaying values of variables or strings or expressions.
This is one of the most useful tasks in Verilog.
Displaying information
Usage: $display(p1, p2, p3,....., pn);
p1, p2, p3,..., pn can be quoted strings or variables or expressions.
The format of $display is very similar to printf in C.
A $display inserts a newline at the end of the string by default.
A $display without any arguments produces a newline.
Operations such as displaying on the screen, monitoring values of nets, stopping, and
finishing are done by system tasks.
We will discuss only the most useful system tasks. Other tasks are listed in Verilog manuals
provided by your simulator vendor or in the IEEE Standard Verilog Hardware Description
Language specification.

Basic Concepts
Strings can be formatted using the specifications
listed in Table.
Example-$display Task
//Display the string in quotes
$display("Hello Verilog World");
-- Hello Verilog World
//Display value of current simulation time 230
$display($time);
-- 230
//Display value of 41-bit virtual address 1fe0000001c at time
200
reg [0:40] virtual_addr;
$display("At time %d virtual address is %h", $time,
virtual_addr);
-- At time 200 virtual address is 1fe0000001c

Basic Concepts
Example - $display Task
//Display value of port_id 5 in binary
reg [4:0] port_id;
$display("ID of the port is %b", port_id);
-- ID of the port is 00101
//Display x characters
//Display value of 4-bit bus 10xx (signal contention) in binary
reg [3:0] bus;
$display("Bus value is %b", bus);
-- Bus value is 10xx
/*Display the hierarchical name of instance p1 instantiated
under the highest-level module called top. No argument is
required. This is a useful feature*/
$display("This string is displayed from %m level of hierarchy");
-- This string is displayed from top.p1 level of hierarchy

Basic Concepts
Example- Special Characters
//Display special characters, newline and %
$display("This is a n multiline string with a %% sign");
-- This is a
-- multiline string with a % sign
Verilog provides a mechanism to monitor a signal when its value changes.
This facility is provided by the $monitor task.
Monitoring information
Usage: $monitor(p1, p2, p3,....., pn);
The parameters p1, p2, ... , pn can be variables, signal names, or quoted strings.
A format similar to the $display task is used in the $monitor task. $monitor continuously
monitors the values of the variables or signals specified in the parameter list and displays all
parameters in the list whenever the value of any one variable or signal changes.
Unlike $display, $monitor needs to be invoked only once.

Basic Concepts
Only one monitoring list can be active at a time. If there is more than one $monitor statement
in your simulation, the last $monitor statement will be the active statement.
The earlier $monitor statements will be overridden.
 Two tasks are used to switch monitoring on and off.
Usage:
$monitoron;
$monitoroff;
The $monitoron tasks enables monitoring, and the $monitoroff task disables
monitoring during a simulation.
Monitoring is turned on by default at the beginning of the simulation and can
be controlled during the simulation with the $monitoron and $monitoroff tasks.
Example- Monitor Statement
//Monitor time and value of the signals clock and reset
//Clock toggles every 5 time units and reset goes down at 10 time units
initial
begin
$monitor($time,
" Value of signals clock = %b reset = %b", clock,reset);
end
Partial output of the monitor statement:
-- 0 Value of signals clock = 0 reset = 1

Basic Concepts
The task $stop is provided to stop during a simulation.
Stopping and finishing in a simulation
Usage: $stop
The $stop task puts the simulation in an interactive mode. The designer can then debug
the design from the interactive mode.
The $finish task terminates the simulation.
Usage: $finish
Example-Stop and Finish Tasks
// Stop at time 100 in the simulation and examine the results
// Finish the simulation at time 1000.
initial // to be explained later. time = 0
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time = 100
#900 $finish; // This will terminate the simulation at time = 1000
end

Basic Concepts
Example- `define Directive
//define a text macro that defines default word size
//Used as 'WORD_SIZE in the code
'define WORD_SIZE 32
//define an alias. A $stop will be substituted wherever 'S appears
'define S $stop;
//define a frequently used text string
'define WORD_REG reg [31:0]
// you can then define a 32-bit register as 'WORD_REG reg32;
Compiler Directives
Compiler directives are provided in Verilog. All compiler directives are defined by using the
`<keyword> construct. We deal with the two most useful compiler directives.
`define
The `define directive is used to define text macros in Verilog.
The Verilog compiler substitutes the text of the macro wherever it encounters a
`<macro_name>.
This is similar to the #define construct in C.
The defined constants or text macros are used in the Verilog code by preceding them with a
` (back tick).

Basic Concepts
Example ìnclude Directive
// Include the file header.v, which contains declarations in the
// main verilog file design.v.
'include header.v
...
...
<Verilog code in file design.v>
...
...
ìnclude
The ìnclude directive allows you to include entire contents of a Verilog source file in
another Verilog file during compilation.
This works similarly to the #include in the C programming language.
This directive is typically used to include header files, which typically contain global or
commonly used definitions

Basic Concepts
Reference
Samir Palnitkar, “Verilog HDL – A guide to Digital
Design and Synthesis”, Pearson, 2003
For Further Studies

Prof. Anand H. D.
M. Tech. (PhD.)
Assistant Professor,
Department of Electronics & Communication Engineering
Dr. Ambedkar Institute of Technology, Bengaluru-56
Email: anandhd.ec@drait.edu.in
Phone: 9844518832

Basic concepts in Verilog HDL

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