Applications - embedded systems

Dr.Y.NARASIMHA MURTHY Ph.D
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UNIT-IV APPLICATIONS –EMBEDDED SYSTEMS
JTAG –FLASH PROGRAMMING
JTAG stands for Joint Test Action Group, which is an IEEE test standard , started in 1985 by a
group of European companies and by 1988, the concept gained momentum in North America
and several companies formed the Joint Test Access Group (JTAG) consortium to formalize the
idea. In 1990, the Institute of Electrical and Electronic Engineers (IEEE) refined the concept and
created the 1149.1 standard, known as IEEE Standard Test Access Port and Boundary Scan
Architecture. The primary application, for which Boundary Scan was initially developed, was to
detect and diagnose manufacturing defects related to connectivity at the board level, such as
stuck-at-0 and stuck-at-1 faults, open solder joints, and shorted circuit nodes. Today, the test
access port defined in IEEE 1149.1 is used for many additional applications, such as in-system
programming, access to built-in self test, on-chip emulation and debug resources, and system
level test.A number of additional standardization efforts related to JTAG / Boundary Scan have
recently been completed (e.g. IEEE 1149.7, IEEE 1500, IEEE 1581) or are under way (e.g. IEEE
P1149.8.1, IEEE P1687, IEEE P1838, SJTAG). Boundary scan is a methodology allowing
complete controllability and observability of the boundary pins of a JTAG compatible device via
software control. This capability enables in-circuit testing without the need of bed-of-nail in-
circuit test equipment.

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The figure explains the structures for input and output pins of a JTAG-compliant device.
During standard operations, boundary cells are inactive and allow data to be propagated through
the device normally. During test modes, all input signals are captured for analysis and all output
signals are preset to test down-string devices. The operation of these scan cells is controlled
through the Test Access Port (TAP) Controller and the instruction register.
The basic operation is controlled through four pins : Test Clock (TCK), Test Mode Select
(TMS), Test Data In (TDI), and Test Data Out (TDO).
The TCK and TMS pins direct signals between TAP controller states. The TDI and TDO pins
receive the data input and output signals for the scan chain. Optionally, a fifth pin, TRST, can be
implemented as an asynchronous reset signal to the TAP controller.
Programming Flash memory through boundary scan has many advantages over other common
programming techniques. Boundary scan programming has limited impact on product design, as
compared to In-Circuit Test (ICT) that requires added test points to access all Flash device pins.
ICT also limits Flash programming to the manufacturing facility, while boundary scan
programming can be done at various test steps as well as in the field for system upgrades.
A limitation of boundary scan Flash programming is the programming time, which is affected by
the number of scan operations needed, the length of the scan path, the maximum TCK frequency
supported by the PCB, the amount of data to be loaded, and burn time. Careful board selection
and design can minimize programming times for Flash memory.

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Programming Flash memory with the use of 1149.1 boundary scan requires that the Flash’s
address, data, and control signals are connected to a boundary scan compliant device. Some
Flash devices support boundary scan, with all necessary signals connected to a TAP : TCK,
TMS, TDI, and TDO. Others require the Flash device to be connected to a boundary scan
compliant device on the PCB that acts as a programming host. Programming a non-boundary
scan Flash device requires data to be scanned through the boundary scan registers of the
surrounding boundary scan devices acting as programming hosts. This requires more TCK
cycles and therefore a longer programming time than directly programming a boundary scan
Flash through its TAP.
For Flash programming, the EXTEST instruction is selected to interact with the memory device.
Typical TCK rates are 1 MHz to 10 MHz, and to program a Flash memory device it is not
uncommon to require millions, or even billions, of TCK cycles. The number of scans to write to
a Flash device depends on the device type, and the boundary scan tool used to apply the address
and program data must know the sequence of events required to control the flash device.
Typical Flash devices require 4 to 8 scans to program one memory location. With Flash memory
device density easily reaching or exceeding 32 M.bit, it is essential for the boundary scan tool
used to control the device to operate at the maximum TCK frequency to minimize programming
time. When using a general purpose DTI as a boundary scan programming tool, itis also
important for the DTI to have deep memory associated with the TDI and TDO pins to store
program data. If the DTI does not have deep enough memory to store all the data to program the
Flash device, there may be overhead with loading multiple pattern sets.
AUDIO CODEC-97 (AC’97) :
AC'97 (Audio Codec '97; also MC'97 for Modem Codec '97) is an audio codec standard
developed by Intel Architecture Labs in 1997. The standard is used in motherboards, modems,
and sound cards. Here the term CODEC is an acronym for Coding and Decoding. AC'97 defines

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a high-quality, 16- or 20-bit audio architecture with surround sound support for the PC. AC'97
supports a 96 kHz sampling rate at 20-bit stereo resolution and a 48 kHz sampling rate at 20-bit
stereo resolution for multichannel recording and playback. AC97 defines a maximum of 6
channels of analog audio output.
In terms of software a Codec is an algorithm or specialized computer program, that reduces the
number of bytes consumed by large files and programs..The Codec will code the data in one
direction of transmission and decodes in another direction of transmission. Alternately the term
CODEC is also used for Compression /Decompression also.
A typical AC ‘97 devices consists of the following parts.
• Audio Codec (often referred to or abbreviated as AC ‘97 or just AC)
• Modem Codec (often referred to or abbreviated as MC ‘97 or just MC)
• Combined Audio/Modem Codec (often referred to or abbreviated as AMC ‘97 or just AMC).
The interfacing of an Audio Codec with a controller is shown below.
The basic features of AC 97 are
Industry Standard 48-pin QFP package and pin out
Up to four analog line-level stereo inputs ; up to two analog line-level mono inputs
High quality pseudo-differential analog CD input
MIC input with 20 dB boost, programmable gain, and AEC reference capability
Dedicated stereo output (LINE_OUT) etc.

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The AC ‘97 Codec performs DAC and ADC conversions, mixing, and analog I/O for audio (or
modem), and always functions as slave to an AC ‘97 Digital Controller, which is typically either
a discrete PCI accelerator or a Controller that comes integrated within core logic chipsets. The
digital link that connects the AC ‘97 Digital Controller to the AC ‘97 Codec, referred to as AC-
link, is a bidirectional, 5-wire, serial time domain multiplexed (TDM) format interface. AC-link
supports connections between a single Controller and up to 4 CODECs on a circuit board and/or
riser card. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming
data streams, each with 20-bit sample resolution.
JPEG encoder
JPEG is a widely used image compression technique. It is used in image processing systems such
as copiers, scanners and digital camera's. These devices often require high-speed image
compression system. To fulfill this need, an IP-block that performs the JPEG decoding is used
in a digital signal processor.
In 1986, the CCITT, ISO, industry and universities started a standardization group, the Joint
Photographic Experts Group (JPEG). The goal for this group was to develop a new image
compression technique. This resulted in an official standard in the beginning of the nineties. This
standard describes the coding and decoding of continues-tone still images. The standard defines
that a number of different coding techniques may be used. This includes both Huffman and
arithmetic coding, which can both be used in differential and non-differential form. The
standard defines also that for both coding techniques a number of different differential cosines
transforms may be used. This has eventually resulted in fourteen different methods for coding a
JPEG image.
The basic idea of data compression is to reduce the data correlation. By applying Discrete
Cosine Transform (DCT), the data in time (spatial) domain can be transformed into frequency
domain. Because of the less sensitivity of human vision in higher frequency, we can compress
the image or video data by suppressing its high frequency components but do no change to our
eye. Block diagram explanation of JPEG encoding is shown below.

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The JPEG decoding is shown below.
A brief description of the JPEG encoder is given in steps below.
Step 1.Reading the pixel value of the original image in RGB color space.
Step 2. Transfer the RGB color space to YCbCr space since the human eyes are sensitive to
luminance than chrominance which can be down sampled (ex. 4:2:0) to save the storage.
Step 3. Transfer the YCbCr space from space domain to frequency domain by discrete cosine
transform (DCT) since the human eyes are sensitive to low frequency than high frequency which
can be hardly quantized to save the storage.
Step 4. Using quantization to decrease the DCT coefficient values required to recode.
Step 5.Encode the bit stream by Huffman coding due to the probability distribution of symbols.
Symbols with high probability will have shorter codelength, which is a good property to decrease
the memory usage.
The Decoding process is explained below.
1. Reading the bit stream and decode by Huffman decoding.
2. De-quantize the quantized DCT coefficient values.
3. Do the inverse DCT (IDCT) to transfer the YCbCr space from frequency domain to space

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domain.
4. Reconstruct the chrominance by up sampling and transfer the YCbCr space to RGB color
space.
5. Save the pixel value to the bitmap in RGB space and output the decompressed image.
MP3 decoder
MP3 is an audio-specific format designed by the Moving Picture Experts Group (MPEG) as part
of its MPEG-1 standard and later extended in MPEG-2 standard. The first MPEG subgroup –
Audio group was formed by several teams of engineers at Fraunhofer IIS, University of
Hannover, AT&T-Bell Labs, Thomson-Brandt, CCETT, and others. MPEG-1 Audio (MPEG-1
Part 3), which included MPEG-1 Audio Layer I, II and III was approved as a committee draft of
ISO/IEC standard in 1991 and finalized in 1992 and published in 1993 (ISO/IEC).
The use in MP3 of a lossy compression algorithm is designed to greatly reduce the amount of
data required to represent the audio recording and still sound like a faithful reproduction of the
original uncompressed audio for most listeners. An MP3 file that is created using the setting of
128 kbit/s will result in a file that is about 1/11 the size of the CD file created from the original
audio source. An MP3 file can also be constructed at higher or lower bit rates, with higher or
lower resulting quality.
MPEG audio coding under the name MP3 has become one of the most popular standards for
digital audio broadcasting and videos. High compression ratios offered by MP3 codecs in various
stand alone players and hand held devices over the last few years has increased its popularity
immensely. Internet users, music lovers who would like to download highly compressed digital
audio files at near CD quality are the most benefited. Psychoacoustic model, Modified Discrete
Cosine Transform (MDCT) and Huffman coding play a vital role in achieving such compression
ratios.
Working of MP3: As a form of compression, MP3 is based on a psycho-acoustic model ,which
recognizes that the human ear cannot hear all the audio frequencies in a recording. The human
hearing range is between 20 Hz to 20 kHz and it is most sensitive between 2 to 4 kHz. When
sound is compressed into an MP3format, an attempt is made to get rid of the frequencies that
cannot be heard. As such , this is known as 'destructive' compression. After compression, the

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information that is eliminated from the audio signal cannot be replaced.When encoding data into
MP3 format, a variety of compression levels can be set. For example, an MP3 file created with
128 k.bit compression will be of a greater quality and larger file size than that of a 56 k.bit
compression. The greater the compression ratio, the lesser is the sound quality.
The complexity of MP3 codec increases while moving from Layer 1 to Layer3. Layer 1
possesses the lowest complexity and is specifically targeted to applications where the complexity
of the encoder plays an important role. Layer 2 requires a more complex encoder as well as a
slightly more complex decoder. Compared to Layer 1, Layer 2 is able to suppress more
redundancy in the signal and applies the psychoacoustic model in more efficient way. Layer 3 is
once again of an increased complexity and is targeted to applications needing the lowest data
rates, by its suppression of the redundant signal and its improved extraction of feebly audible
frequencies using its filter.
Decoding of MP3 audio is defined in the ISO standard. Each frame is made up of 1152 samples
and there is always a header attached to each of the frames associated in the MP3 file. Content in
the header and side information for a particular frame is necessary so that decoding is done
correctly.
The first and foremost thing in the decoding procedure is the synchronization of the decoder to
the incoming bit stream. Synchronisation is the process of finding the position of the first header
and the subsequent ones. Once this is done, the organization of the encoded data is completely
known and the decoding procedure can be performed smoothly. The block diagram below
gives an idea on the procedure. Frame unpacking constitutes finding the bit stream header,
decoding side information, decoding scale factors and decoding the Huffman data.
Reconstruction block constitutes re-quantizing and reordering the spectrum. Inverse mapping
constitutes joint stereo processing if applicable, alias reduction, synthesis via IMDCT and poly
phase filter bank, and out comes the PCM samples.

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Frame unpacking constitutes finding the bit stream header, decoding side information, decoding
scale factors and decoding the Huffman data. Reconstruction block constitutes re-quantizing and
reordering the spectrum.Inverse mapping constitutes joint stereo processing if applicable, alias
reduction, synthesis via IMDCT and polyphase filter bank, and out comes the PCM samples.
MPEG Audio Compression :
MPEG (Motion Picture Experts Group) is the international standard for multimedia. It
incorporates both audio and video encoding at a range of data rates. MPEG audio and video are
the standard formats used in Video CDs and DVDs. The lowest data rate supported forMPEG-1
mono audio is 32 kbps. Sample rates of 32 kHz, 44 kHz (audio CD) and 48 kHz (Digital Audio
Tape) are supported.
MPEG is a lossy compression, which means, some audio information is certainly lost using these
compression methods. This loss can hardly be noticed because the compression method tries to
control it. By using several complicated and demanding mathematical algorithms it will only lose
those components of sound that are hard to be heard even in the original form.This leaves more
space for information that is important. This way it is possible to compress audio up to 12 times
which is really significant. Due to its quality MPEG audio became very popular.
The bit stream inside an MP3 file contains frames with the following parts
Header
Side information
Main data
Ancillary data.
Header is always 32 bits or 4 bytes and the information in the header confirms the authenticity of
an MP3 file. Location of each header does not always need to be at the beginning of the frame.
Therefore each header starts with a syncword to mark its position in an MP3 file.

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Side information can either be 17 bytes if it is a single channel or 32 bytes if it is a dual channel.
Side information always immediately follows the header. Basically, it contains all the relevant
information to decode the main data. For example it contains the main data begin pointer, scale
factor selection information, Huffman table information for both the granules etc.
Main data need not always follows the side information. It can be divided in such a way that a
part of the main data can be located in the current frame and the other part can be found in the
previous frame. Details on how the main data is organized can be known only after extracting the
side information. It is always necesary to look at least three frames at a time to get some clear
understanding of the bit stream.
Ancillary data can be defined by the user and the exact number of bits is not explicitly
mentioned. It starts after the Huffman coded bits. The distance between the end of the Huffman
coded bits and the location in the bit stream, where the next frame’s main data begin pointer
points to, is the number of ancillary bits .
INTERFACING LEDs TO ARM 7 CONTROLLER- (LPC2148 )
Light Emitting Diodes (LEDs) are popularly used display components used to indicate the ON
and OFF state of a system. These are also used to realize various counters like binary counters
experimentally. These LEDs can be easily interfaced with the Port pins of any Microcontroller
by using current limiting resistors of the order of 220 Ohms.
The diagram below shows the interfacing of LED array to the Port1 pins of LPC2148 ARM 7
microcontroller.

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PROGRAM -1
This program blinks the LEDs continuously with a small delay. The LEDs are connected to the
Port1 pins P1.24 to P1.31 and the these pins are configured as General Purpose output pins.
#include<lpc2148.H> //LPC2148 Header
void delay()
{
for(int i=0x00;i<=0xff;i++)
for(int j=0x00;j<=0xFf;j++) ; // Delay program
}
void main()
{
PINSEL2 = 0X00000000; // Set P1.24 TO P1.31 as GPIO
IO1DIR = 0XFF000000; //Port pins P1.24 to P 1.31 Configured as Output port.
while(1) //Infinite loop
{
IO1SET=0XFF000000; // Pins P1.24 to P1.31 goes to high state
delay();
IO1CLR=0XFF000000; // Pins P1.24 to P1.31 goes to low state
delay() ;

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}
}
PROGRAM – 2
This program glows LEDs alternately by sending 55H and AAH through the port1 Pins.
# include <LPC214X.H> //LPC2148 HEADER
void delay(void) // Delay Program
{
unsigned int i;
i=0xffffff;
while(i--);
}
int main(void)
{
PINSEL2=0x0000; // Port 1 is I/O
IODIR1 = 0XFF <<24 ; // Port Pins P1.24 to P1.31 as Output Pins
while(1) // Infinite loop
{
IOSET1=0X55<<25 ; // P1.25,P1.27,P1.29 & P1.31 LEDs will Glow
delay() ; // Call delay function
IOCLR1= 0X55 <<25 ; // P1.25,P1.27,P1.29 &P1.31 LEDs will be off
IOSET1=0XAA<<24 ; //P1.24,P1.26,P1.28 &P1.30 LEDs are Glow
delay () ; // Call delay function
IOCLR1=0XAA<<24 ; // P1.24,P1.26,P1.28 &P1.30 LEDs are off
}
}
INTERFACING A RELAY TO ARM 7 CONTROLLER- (LPC2148 )
Relays are devices which allow low power circuits to switch a relatively high Current/ Voltage
ON/OFF. A relay circuit is typically a smaller switch or device which drives (opens/closes) an
electric switch that is capable of carrying much larger current amounts.

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Figure below shows the interfacing of the Relay to ARM controller. When the input is
energized, the relay turns on and the '+' output is connected to +12v. When the relay is off, the '+'
output is connected to Ground. The '-' output is permanently wired to Ground.
The relay is interfaced to P0.30 Pin through an Opto-isolator. This opto-isolator protects the port
pin from damage due to any high currents .The opto-isolator consists of a pair of an LED and a
Photo transistor as shown in the diagram. The power transistor is used at the input. So, when the
input is high , the output of the transistor is LOW and the relay is in OFF state .Similarly when
we apply a low to the transistor ,the out put is high and the relay is ON.
Interfacing Circuit.

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PROGRAM
The following program configures the P0.30 pin as an out port. When a low signal is sent
through this pin to the relay the relay is switched ON and when a high signal is sent the relay is
switched OFF.A constant delay is created between the two events and hence the relay switches
ON and OFF in regular intervals of time.
# include <LPC214X.H> //LPC2148 HEADER
# define relay 1<<30 // ASSIGN P0.30 Pin to RELAY input PIN
void DELAY(void) // Delay function
{
unsigned int i;
i=0xffffff;
while(i--) ;
}
int main(void) // Main program
{
IODIR0=1<<30 ; // P0.30 Port Pin as Outport

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while(1) //INFINITE LOOP
{
IOSET0=1<<30 ; //SWITCH OFF RELAY
DELAY() ; //CALL DELAY
IOCLR0=1<<30 ; // SWITCH ON RELAY
DELAY() ; // CALL DELAY
} // REPEAT LOOP
}
INTERFACING A STEPPER MOTOR TO ARM 7 CONTROLLER- (LPC2148 )
A stepper motor is a brushless, synchronous electric motor that converts digital pulses into
mechanical rotation in steps. Every revolution of the stepper motor is divided into a discrete
number of steps, and for each pulse it receives the motor rotates through one step.
Fig below shows the interface of the Stepper Motor to ARM 7 controller. The stepper motor is
connected to Microcontroller using a ULN2003 driver IC. The ULN driver IC is connected to
the Port1 pins P1.19 to P1.22 pins. So as the microcontroller gives pulses with a particular
frequency to ULN2003, the motor is rotated either in clockwise or anticlockwise.

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PROGRAM
This program first configures the ARM Port1 as a GPIO and also as an out port. The sequence
code is sent to the driver IC using these port pins. A suitable delay is incorporated between each
step rotation. By applying the code in the reverse order, the stepper motor can be rotated in the
anticlockwise direction.
# include <LPC214X.H> // LPC2148 HEADER
void delay_ms() ; // Delay function
void main() ; // Main program starts
{
PINSEL2 = 0X00000000; // Set P1.19 TO P1.22 as GPIO
IO1DIR=0x000000F0 ; // Set Port 1 as out port
while(1) // Infinite Loop
{
IO1PIN = 0X00000090; // Send the code1 for phase 1
delay_ms() ; // Call Delay
IO0PIN = 0X00000050 ; // Send the code 2 for phase 2
IO1PIN = 0X00000060 ; // Send the code 3 for phase 3
IO1PIN = 0X000000A0 ; // Send the code 3 for phase 3
}
}
void delay_ms() // Delay function program
{
int i,j ;
for(i=0;i<0x0a;i++)

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for (j=0;j<750;j++) ;
}
INTERFACING OF DAC-ARM LPC2148
A digital-to-analog converter is a device for converting a digital signal into to an analog signal
(current or voltage ). Digital-to-Analog Converters are the interface between the abstract digital
world and the analog real world. Simple switches, a network of resistors, current sources or
capacitors may be used to implement this conversion. A DAC inputs a binary number and
outputs an analog voltage or current signal.
The Microchip Technology Inc. MCP4921 is 2.7 – 5.5V, low-power, 12-Bit Digital-to-Analog
Converter (DAC) with SPI interface. The MCP4921 DACt provides high accuracy and low
noise performance for industrial applications where calibration or compensation of signals is
required.
With an SPI connection there is always one master device (usually a microcontroller) which
controls the peripheral devices. Typically there are three lines common to all the devices,
Master In Slave Out (MISO) - The Slave line for sending data to the master,
Master Out Slave In (MOSI) - The Master line for sending data to the peripherals,
Serial Clock (SCK) - The clock pulses which synchronize data transmission generated by the
master, and
Slave Select pin - the pin on each device that the master can use to enable and disable specific
devices.
When a device's Slave Select pin is low, it communicates with the master. When it's high, it
ignores the master. In SPI, the clock signal is controlled by the master device LPC2148 . All
data is clocked in and out using this pin. These lines need to be connected to the relevant pins on
the LPC21xx processor. Any unused GIO pin can be used for CS, instead pull this pin high.
Conversion speed is the time it takes for the DAC to provide an analog output when the digital
input word is changed. The MCP4291 DAC - SPI connections with LPC21xx have four I/O
lines (P0.4 – P0.7) required. The analog output is generated by using these four lines.

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PROGRAM
#include <LPC2148.H> // 2148 Header
#include "SPIsw.h"
unsigned long DACval, DACreg;
int main (void) // Main program
{
PINSEL0 = 0 ; // Port 0 as GPIO
PINSEL1 = 0x0000 ; // Port 0 as Outport
PINSEL2 & = 0x0000000C;
SPI_ init (&IOPIN0,29/*CS*/, 5/*MISO*/, 6/*MOSI*/, 4/*SCK*/, 0/*CPOL*/, 0/*CPHA*/) ;
// Set output voltage
DAC val = 2047 ; // Range [0..4095]
DAC reg = DACval | 0x7000 ;
SPI_enable () ; // Enable SPI port
SPI_char ((DACreg >> 8) & 0x00FF);
SPI_char (DACreg & 0x00FF) ;
SPI_disable () ; // Disable SPI port
while (1) ; // Infinite Loop
}

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INTERFACING ADC –LPC2148
LPC2148 controller has two on n-chip ADCs. In the present program the ADC0 with channel 3
is used and configured to convert the analog input signal into its equivalent digital output.The
configuring of on chip ADC is shown below.
PROGRAM
#include "lpc214x.h" // This example assumes that PCLK is 12Mhz!
int main(void)
{ // Initialise ADC 0, Channel 3
adcInit0_3() ; // Constantly read the results of ADC0.3
int results = 0;
while (1)
{
results = adcRead0_3();
}
} // Initialise ADC Converter 0, Channel 3
void adcInit0_3(void)

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{ // Force pin 0.30 to function as AD0.3
PCB_PINSEL1 = (PCB_PINSEL1 & ~PCB_PINSEL1_P030_MASK) |
PCB_PINSEL1_P030_AD03; // Enable power for ADC0
SCB_PCONP |= SCB_PCONP_PCAD0; // Initialise ADC converter
AD0_CR = AD_CR_CLKS10 // 10-bit precision
| AD_CR_PDN // Exit power-down mode
| ((3 - 1) << AD_CR_CLKDIVSHIFT) // 4.0MHz Clock (12.0MHz / 3)
| AD_CR_SEL3; // Use channel 3
}
int adcRead0_3(void) // Read the current value of ADC0.3
AD0_CR &= ~(AD_CR_START_MASK | AD_CR_SELMASK); // Deselect all channels
and stop all conversions
{
AD0_CR |= (AD_CR_START_NONE | AD_CR_SEL3); // Select channel 3
AD0_CR |= AD_CR_START_NOW; // Manually start conversions (rather than waiting on
an external input)
while (!(AD0_DR3 & AD_DR_DONE)) ; // Wait for the conversion to complete
return ((AD0_DR3 & AD_DR_RESULTMASK) >> AD_DR_RESULTSHIFT);
// Return the processed results
}
INTERFACING A SEVEN SEGMENT DISPLAY–LPC21XX
A seven segment display can be used to interface with LPC21XX microcontroller using the
GPIO lines. By using one seven segment display module along with LPC21XX ,a Hex counter
which counts 0 to F can be designed. By interfacing two Seven segment displays, a Hex counter
which counts 00 to FF can be designed. The LSB segment is interfaced to Port1 GPIO
lines(P1.16 to P1.22) and MSB module is interfaced to Port0 GPIO lines(Port0.16 to Port0.22) as
shown in the circuit diagram.

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PROGRAM
#include<lpc21xx.h>
unsigned char seg[16] ={0x40,0x79,0x24,0x30,0x19,0x12,0x02,0x78,0x00,0x10,0x08,
0x03,0x46,0x21,0x06,0x0e};
unsigned char seg_val,seg_val1;
unsigned char count,count1;
unsigned long int var,var1;
void main(void)
{ unsigned long int k;
PINSEL0=0X00000000; // Select Port 0 pins as GPIO lines

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PINSEL1=0X00000000; // Select Port 1 pins as GPIO lines
IODIR0 = 0X00FF0000; // Configure the required pins of Port 0 as output pins
IODIR1 = 0X00FF0000; // Configure the required pins of Port 1 as output pins
for (count=0;count<=15;count++) // COUNT FOR MSB
{ IOCLR1 = var;
seg_val = seg[count];
var = seg_val;
var = var<<16;
IOSET1 = var;
for(count1=0;count1<=15;count1++) // COUNT FOR LSB
{ IOCLR0=var1;
seg_val1=seg[count1];
var1=seg_val1;
var1=var1<<16;
IOSET0=var1;
for(k=0;k<50000;k++);
} // End for loop
} // End for loop
} // End main.

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S INTERFACING OF 2X16 LCD MODULE - LPC21XX
The ARM7 LPC21xx processor is interfaced to the 2x16 LCD mpdule in 4-bit mode .The
interfcae diagram is shown below.The four data pins are connected with 4 data bits (P0.19 –
P0.22 pins to bits D4-D7), address bit (RS-P0.16), read/write bit (R/W-P0.17) and control
signal (E-P0.18) to make LCD display complete.The pins D0,D1,D2,D3 are left free with out
any connections.
16X 2 LCD is a 16 pin module . In which pins 1 &16 are grounded, 2 &15 are given to VCC
and 3rd
pin is given to potentiometer in order adjust the contrast of LCD. Pins 4, 5 & 6
corresponds to RS, R/W & EN respectively. Pins 7 to 14 are data lines from D0 to D7
respectively. Here the LCD is used in 4 bit mode i.e. upper 4 bits are used to transfer the data
with MSB first and LSB next. Port 0 pins i.e. from P0.16 to P0.22 are used for both data and
control signals. The interfacing diagram of 16X2 LCD is shown below.
PROGRAM
#include <LPC21xx.H>
long unsigned int data,temp1,temp2;
unsigned char *ptr,data_array[] = "SSBN DEGREE & PG COLLEGE, ATP";
void main()
{
int i=0;

yayavaram@yahoo.com
24
PINSEL0 = 0x00000000; // Select Port 0 pins as GPIO lines
IODIR0 = 0x00ff0000; // Configure the required pins of Port 0 as output pins
lcd_init(); // LCD initialization
delay(2500); // Delay
ret_home(); // Cursor to return home
clr_disp(); // Clear display
ptr = &data_array[0];
for(i=1;i<sizeof(data_array);i++)
{
if(i == 17)
{ temp1 = 0xc0; // Goto 2nd line in the LCD
lcd_com(); // Byte to nibble conversion of LCD command
delay(800);
} // End if
data = *ptr;
lcd_data(); // Byte to nibble conversion of LCD data
ptr++;
} // End for loop
} // End main
void lcd_init(void) // Initialization of LCD
{
temp2=0x30; // Assign command to temp2
temp2=temp2<<16; // Shift the data by 16 bits left
cmd_wrt(); // Command write subroutine
temp1 = 0x28; // Command for LCD to function in 4 bit mode
lcd_com();
delay(800);

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25
temp1 = 0x0c; // Command for display on, cursor off
lcd_com();
delay(800);
temp1 = 0x06; // Command for cursor increment
lcd_com();
delay(500);
temp1 = 0x80; // Command to force the cursor to beginning of 1st line
lcd_com();
delay(800);
}
void delay(unsigned int j) // Delay subroutine
{ unsigned int k;
for(k=0;k<j;k++);
}
void clr_disp(void) // To clear LCD display
{ temp1 = 0x01;
lcd_com();
delay(320);
}
void ret_home(void) // To return home
{ temp1 = 0x02;
lcd_com();
delay(320);
}
void lcd_com(void) // Byte to nibble conversion of LCD command
{ temp2= temp1 & 0x00f0;
temp2=temp2<<16;
cmd_wrt();
temp2 = temp1 & 0x000f;
temp2 = temp2 << 20;
cmd_wrt();
}
-------------------xxxxxxx-------------
Acknowledgment: I thank all the people without whose contribution ,this class notes would
have not been possible ,especially Pantech Solutions website .

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