Racyics

This week we welcomed our scholarship recipients to our Dresden office🎓 On Monday we had the pleasure of hosting students from the #Deutschlandstipendium on site to give them a glimpse of our company, research projects and learn more about IC Design. The students are currently studying the second semester of their diploma in Electrical Engineering at Technische Universität Dresden and are spending their first days of the semester at Racyics to see our office and company. The day started with the students meeting our line managers, who shared their experiences and gave them a deeper understanding of their exciting roles. After that, they learned about the research projects we’re working on and visited our lab, where they saw firsthand how we bring-up and validate our chip designs. The day wrapped up with an IC Design training session, followed by lunch, where the students had the chance to network with our working students and learn more about the semiconductor industry. A big thank you to everyone who made this visit possible. It was a fantastic opportunity to connect with the young students. We’re already looking forward to next year! #Deutschlandstipendium #TUDresden #earlycareers #Innovation #Racyics #ICDesign

Racyics supports customers at every stage of the design process of integrated circuits. Today we introduce our Physical Implementation Line, contributing to 𝗰𝗵𝗶𝗽 𝗱𝗲𝘀𝗶𝗴𝗻𝘀 𝗱𝗼𝘄𝗻 𝘁𝗼 𝟯 𝗻𝗺 for automotive, consumer and communication applications. 👥 What They Do: The team takes care of the whole RTL2GDS flow: • It starts with Synthesis turning complex RTL code into logic gates under consideration of timing, floorplan and power • During Floorplanning and Placement, the chip size and physical hierarchies are defined. Locations of interfaces, power domains, macros and standard cell areas are planned using expert knowledge for achieving the best PPA • Our Clock Tree Synthesis creates a robust clock network across the entire chip that keeps all relevant parts in sync • Timing- and SI-aware Signal Routing and Chip Finishing conclude the design process • RTL code and netlists are frequently compared throughout the flow by Logical Equivalence Checks • We perform extensive Verifications including PV, STA, EM, IR Drop and ESD checks to enable high yield for manufacturing and ensure functionality • With custom IC Package Design and Package Co-Simulation we develop specific customer solutions which fulfill cost, size and thermal requirements 🌐 Why Racyics? • One partner addressing RTL-to-GDSII block-level implementation for mixed signal analog-on-top design to hierarchical multi-million gate designs • Proven track record in advanced FDSOI and FinFet technology nodes down to 3 nm • Low-power implementation experience including DVFS and PSO • Continuous Power Performance Area (PPA) optimization to ensure the best solution for your design target • Close research cooperation with universities, therefore always up to date with the latest developments in fields like cryoelectronics or Edge-AI accelerators • Design experience ranging from MPW research chips up to complex full-mask SoCs • Our ABX® platform enables world-leading energy efficiency by fully leveraging the 22FDX® Adaptive Body Bias capabilities. With silicon-proven expertise, we do Minimum Energy Point studies and support you in finding the best PPA for your design • Design experience in functional safety-critical designs including 6-sigma signoff • No tool vendor limitations: Racyics supports all industry EDA tools • Cloud-based Design Environment makeChip enabling collaborative work with our customers • Our experienced engineers follow ISO standards, quality milestones and detailed checklists. This way, we ensure first time right designs with optimum PPA If you are interested in partnering with Racyics, feel free to contact us. We look forward to collaborating with you! 💡 What you see: The GIF shows the design of the 22FDX® rapid adaption kit, a complete RISC-V processor design. This kit is exclusively offered to our customers at makeChip - a cloud-based IC design platform - and aims to reduce time to market. #asic #semiconductorindustry #semiconductor #innovation #technology

📢 DATE is coming, and Racyics will be there! 📅 31st March – 2nd April 2025 📍 Lyon, France We are proud sponsors of Design, Automation and Test in Europe Conference (DATE) 2025, and our colleagues Florian Bilstein, Dr.-Ing. Mikail Yayla, and Andrea Garcia will be there. It’s a great opportunity to connect with students, PhDs, and researchers. 🔹 Panel on Future Career Perspectives Join us for a panel discussion on career paths in IC Design and the industry. Our colleague and SoC Design Team Lead Dr.-Ing. Mikail Yayla will talk about his experiences and how his path led him to Racyics. 🔹 Company Presentation & Speed Dating Meet our talent attraction specialist Andrea Garcia. We will present our company, and you’ll have the chance to connect with us to explore career opportunities. 🔹 Mentoring Coffee Breaks Join us during Tuesday morning coffee break and connect with Mikail and Andrea on discussing career advice, industry trends, and insights into working in the semiconductor industry. 🔹 Exhibition Area Join us at the exhibition area and chat and connect with our Racyics Design Services, IP Products, makeChip and job opportunities. We look forward to meeting you there! 🌍 #Racyics #DATE2025 #Innovation #Networking #YoungProfessionals #YPP #Lyon #asic #semiconductorindustry #semiconductor #technology

Racyics introduces its new ULP Power and Clock Generation IP for GlobalFoundries® 22FDX®. The ULP Power and Clock Generation IP is designed to complement our Adaptive Body Biasing ABX platform https://lnkd.in/esdEZDnW. It is a power management system that integrates all essential components to ensure efficient SoC operation. With our ULP IP, you have all components needed for the development of energy-efficient SoCs in GlobalFoundries® 22FDX®, including reference voltage generation, variable core power supplies and versatile clock generation, everything enabled for easy integration. Our ULP IP solution simplifies power management and can be customized for a wide range of applications. Key features include: Supply and Reference Voltages: ☑️ 0.8 V supply for always-on logic ☑️ 0.4-0.9 V variable supply, up to 250 mA load ☑️ Seamless switching between LDO and DC / DC ☑️ 0.6 V voltage reference for MRAM Clock Generation: ☑️ Ultra-low power 50 MHz clock generator from 32 kHz reference clock ☑️ PLL up to 500 MHz Control Logic: ☑️ Simple handshake protocol for mode selection ☑️ APB interface for detailed configuration ☑️ Reference clock failure detection and safe shutdown handling #Racyics #Innovation #semiconductor #technology #ULP #IP #intellectualproperty #GlobalFoundries #22FDX

📢 Featured in GlobalFoundries Blog We are excited to be featured in a recent Global Foundries® blog! The Racyics ABX Platform for GlobalFoundries 22FDX® technology enables ultra-low voltage operation down to 0.4V by means of adaptive body biasing (ABB), compensating for process, voltage and temperature (PVT) variations to ensure reliable and consistent performance. This exemplarily results in up to 9x performance increase and up to 75% leakage current reduction for ULV conditions, where logic designs at Minimum-Energy-Point are implemented. ☑️ Comprehensive IP platform for ultra-low power and high-performance applications with full ABB enablement. ☑️ Easy-to-use turnkey ABB solution based on standard design flow and sign-off. ☑️ Includes 𝗔𝗕𝗕 𝗚𝗲𝗻𝗲𝗿𝗮𝘁𝗼𝗿, 𝗦𝘁𝗮𝗻𝗱𝗮𝗿𝗱 𝗖𝗲𝗹𝗹𝘀, 𝗗𝘂𝗮𝗹-𝗥𝗮𝗶𝗹 𝗦𝗥𝗔𝗠 and 𝗦𝗶𝗻𝗴𝗹𝗲-𝗥𝗮𝗶𝗹 𝗦𝗥𝗔𝗠 based on Racyics logic-based bitcell for ULV operation. ☑️ All IPs are silicon proven and 𝗿𝗲𝗮𝗱𝘆 𝗳𝗼𝗿 𝗽𝗿𝗼𝗱𝘂𝗰𝘁𝗶𝗼𝗻. For more details, visit https://lnkd.in/esdEZDnW to explore our IP Product Sheets. #GF #semiconductor #ICDesign #Innovation #IP #Racyics #22fdx

#embeddedworld 2025 has reached its midpoint, and our team is motivated to connect with partners, customers, and anyone interested in learning more about Racyics' offerings. Stop by our booth in Hall 4, Booth 4-573 at embedded world Exhibition&Conference to discuss your upcoming projects and explore how we can help you with your next analog, mixed-signal and digital IC and custom ASIC. #ew25 #europe #semiconductor #asic #soc

We invite you to visit our booth at the embedded world Exhibition&Conference, located in Hall 4, Booth 4-573! As Europe’s leading design partner for mixed-signal SoC design, we will be highlighting our services and capabilities and showcasing our unique strengths, including: ➡️ Proven Track Record in Advanced Nodes, down to 3 nm feature size ➡️ A true European Supply Chain for low and mid-volume ASIC products ➡️ ABX® Platform efficiency for IoT and Edge-AI applications Platform, enabling world-leading energy efficiency ➡️ Advanced Packaging Solutions, including UCIe-based chiplet solutions ➡️ Collaborative Work enabled through our Cloud-based Design Environment, makeChip Our colleagues, Florian Bilstein, Marcus Pietzsch and Patrick Döll, will be there to demonstrate our services and latest innovations, and discuss your specific needs. Whether you are interested in Turnkey ASIC, Design Services, IP Products, or Foundry Access, we invite you to explore a potential partnership with us. Contact us to arrange a meeting or visit us at Hall 4, Booth 4-573. We look forward to connecting with you at the Embedded World Conference. #ew25 #innovation #asic #fdsoi #Europe #Semiconductors

Many thanks to Jörg Schreiter for putting up the banner in our Racyics Dresden office. This Sunday the election for the German Bundestag takes place. At Racyics, democracy, freedom and diversity are core values. We vote for a Germany that is global, innovative and open. A perspective and future for everyone. 𝗚𝗢 𝗩𝗢𝗧𝗘!

Racyics is pleased to support universities with guest lectures once again! For us at Racyics, it is always a great opportunity to support the next generation of engineers with insights into industry-relevant topics. Over the last two months, we have contributed to this with several guest lectures at German universities. Our colleague Dr.-Ing. Mikail Yayla gave a lecture on "SoC Concepts" at TU Dortmund University, while Sorrasit Bunluehan delivered a session on "SoC Design" at Karlsruhe Institute of Technology (KIT). Their talks covered key topics in the chip industry and its applications. On the other hand, Shruthi keshava Hegde and Thomas Haack presented “Hierarchical DFT Concepts for Complex SoCs" focusing on testing and reliability in complex SoC designs at Technische Universität Chemnitz and Hochschule für Technik und Wirtschaft Dresden respectively. We really appreciate the professors and organizers who made these lectures possible. Special thanks to Kai Unger, Jens Becker (Academic Councillor, Dr.-Ing.), and Prof. Juergen Becker at KIT, and to Christian Hakert (Postdoc, Dr.-Ing.) and Prof. Jian-Jia Chen at TU Dortmund for their excellent support. A huge thanks to Prof. Jens Schönherr at Hochschule für Technik und Wirtschaft Dresden for giving us the chance to speak in his course, and to Prof. Werner Wolf and Erik Markert at TU Chemnitz for offering us the opportunity to be a part of their lecture. And finally, thank you to all the students who attended! If you missed it, don't worry - we're looking forward to the next opportunity to present at universities and give insights into our work - stay tuned! If you are interested in Racyics, please take a look at our open positions here: https://lnkd.in/dDpHgbm #HTWDresden #DFT #TUChemnitz #KIT #TUDortmund #Innovation #KnowledgeSharing #Lecture #Students #futureleaders

Supporting the young talents and engineers of tomorrow 🎓 The #Deutschlandstipendium shows the importance of supporting academic excellence and talented students. Once again, Racyics participated at Technische Universität Dresden as a sponsor of the #Deutschlandstipendium. Last week, we met our 12 scholarship recipients in the Electrical Engineering field, and this week, we were at Technische Universität Darmstadt, where we had the opportunity to connect with another scholarship recipient and had interesting conversations about their future ambitions and microelectronics. These students will become the next generation of engineers, and we are committed to supporting them as they pave the way in both their studies and professional career. Programs like this are key in contributing to their future and development and we are proud to be part of this initiative. Many thanks to Franziska Plathner and her whole team for organizing such a great event! 📷 Hans-Georg Unrau #Deutschlandstipendium #Racyics #TUDresden #ShapingTheFuture #EngineeringExcellence