System Verilog (Tutorial -- 2X1 Multiplexer)

Jun 23, 20200 likes1,500 views

Denise Wilson

An introductory tutorial using a 2X1 Multiplexer to illustrate basic module and test bench development in Verilog.

A 2 X 1 M U LT I P L E X E R
S Y S T E M V E R I L O G

S Y S T E M V E R I L O G
A 2 X 1 M U LT I P L E X E R
This Tutorial covers:
logic — four-state integer type where the four possible states are:
• 1 (high; True);
• 0 (low; False;
• x (unknown) — this means that the state is unknown; Verilog initializes four-state
types to X.
• z (high impedance) — this means that the state is disconnected and is essentially
“floating.”
output, input — describe the ports associated with a module and
provides a way to communicate with a module
assign — continuous assignment statement in system verilog
module — for simulation of digital circuits in software and synthesis
of digital circuits in hardware

S Y S T E M V E R I L O G
A 2 X 1 M U LT I P L E X E R
module mux2_1(out, i0, i1, sel);
output logic out;
input logic i0, i1, sel;
assign out = (i1 & sel) | (i0 & ~sel);
endmodule
Creates a block of code which can be
instantiated (i.e. used) as many times as
needed in highboy other files in a
design. This module is named mux2_1
and has four ports (out, i0, i1, sel)
which allow other modules to
communicate with it.

S Y S T E M V E R I L O G
A 2 X 1 M U LT I P L E X E R
module mux2_1(out, i0, i1, sel);
output logic out;
input logic i0, i1, sel;
assign out = (i1 & sel) | (i0 & ~sel);
endmodule
out is an output of the module
mux2_1. out is of the variable type
logic and can have four possible
values: z, x, 0, or 1
i0, i1, sel1 are inputs to the module
mux2_1. These three inputs are also of
the variable type logic and can have
four possible values: z, x, 0, or 1

S Y S T E M V E R I L O G
A 2 X 1 M U LT I P L E X E R
module mux2_1(out, i0, i1, sel);
output logic out;
input logic i0, i1, sel;
assign out = (i1 & sel) | (i0 & ~sel);
endmodule
assigns out
the value of
(i1*sel) + (i0*sel’)
where * or & indicates AND;
+ or | indicates OR;
’ (~) indicates NOT (INVERT)

S Y S T E M V E R I L O G
A 2 X 1 M U LT I P L E X E R
module mux2_1_testbench();
logic i0, i1, sel;
logic out;
mux2_1 dut (.out, .i0, .i1, .sel);
initial begin
sel=0; i0=0; i1=0; #10;
sel=0; i0=0; i1=1; #10;
sel=0; i0=1; i1=0; #10;
sel=0; i0=1; i1=1; #10;
sel=1; i0=0; i1=0; #10;
sel=1; i0=0; i1=1; #10;
sel=1; i0=1; i1=0; #10;
sel=1; i0=1; i1=1; #10;
end
endmodule
Creates variables i0, i1, sel, and out of
variable type logic
Creates a block of code that can be used to
simulate another module (in this case,
mux2_1_testbench() will simulate the
mux2_1 created on the preceding slides)
Sets up the mux2_1 for testing/simulating
and names it dut.

S Y S T E M V E R I L O G
A 2 X 1 M U LT I P L E X E R
In this introductory tutorial,
we have created a 2X1
multiplexer in System Verilog
and created a testbench to
simulate all possible input
combinations in ModelSim.
out
i0
i1
sel
Click here for
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Welcome to the May 2025 edition of WIPAC Monthly celebrating the 14th anniversary of the WIPAC Group and WIPAC monthly. In this edition along with the usual news from around the industry we have three great articles for your contemplation Firstly from Michael Dooley we have a feature article about ammonia ion selective electrodes and their online applications Secondly we have an article from myself which highlights the increasing amount of wastewater monitoring and asks "what is the overall" strategy or are we installing monitoring for the sake of monitoring Lastly we have an article on data as a service for resilient utility operations and how it can be used effectively.

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Agile methodologies have transformed organizational management by prioritizing team autonomy and iterative learning cycles. However, these approaches often lack structured mechanisms for knowledge retention and interoperability, leading to fragmented decision-making, information silos, and strategic misalignment. This study proposes an alternative approach to knowledge management in Agile environments by integrating Ikujiro Nonaka and Hirotaka Takeuchi’s theory of knowledge creation— specifically the concept of Ba, a shared space where knowledge is created and validated—with Jürgen Habermas’s Theory of Communicative Action, which emphasizes deliberation as the foundation for trust and legitimacy in organizational decision-making. To operationalize this integration, we propose the Deliberative Permeability Metric (DPM), a diagnostic tool that evaluates knowledge flow and the deliberative foundation of organizational decisions, and the Communicative Rationality Cycle (CRC), a structured feedback model that extends the DPM, ensuring long-term adaptability and data governance. This model was applied at Livelo, a Brazilian loyalty program company, demonstrating that structured deliberation improves operational efficiency and reduces knowledge fragmentation. The findings indicate that institutionalizing deliberative processes strengthens knowledge interoperability, fostering a more resilient and adaptive approach to data governance in complex organizations.

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In this paper, the cost and weight of the reinforcement concrete cantilever retaining wall are optimized using Gases Brownian Motion Optimization Algorithm (GBMOA) which is based on the gas molecules motion. To investigate the optimization capability of the GBMOA, two objective functions of cost and weight are considered and verification is made using two available solutions for retaining wall design. Furthermore, the effect of wall geometries of retaining walls on their cost and weight is investigated using four different T-shape walls. Besides, sensitivity analyses for effects of backfill slope, stem height, surcharge, and backfill unit weight are carried out and of soil. Moreover, Rankine and Coulomb methods for lateral earth pressure calculation are used and results are compared. The GBMOA predictions are compared with those available in the literature. It has been shown that the use of GBMOA results in reducing significantly the cost and weight of retaining walls. In addition, the Coulomb lateral earth pressure can reduce the cost and weight of retaining walls.

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The TRB AJE35 RIIM Coordination and Collaboration Subcommittee has organized a series of webinars focused on building coordination, collaboration, and cooperation across multiple groups. All webinars have been recorded and copies of the recording, transcripts, and slides are below. These resources are open-access following creative commons licensing agreements. The files may be found, organized by webinar date, below. The committee co-chairs would welcome any suggestions for future webinars. The support of the AASHTO RAC Coordination and Collaboration Task Force, the Council of University Transportation Centers, and AUTRI’s Alabama Transportation Assistance Program is gratefully acknowledged. This webinar overviews proven methods for collaborating with USDOT University Transportation Centers (UTCs), emphasizing state departments of transportation and other stakeholders. It will cover partnerships at all UTC stages, from the Notice of Funding Opportunity (NOFO) release through proposal development, research and implementation. Successful USDOT UTC research, education, workforce development, and technology transfer best practices will be highlighted. Dr. Larry Rilett, Director of the Auburn University Transportation Research Institute will moderate. For more information, visit: https://aub.ie/trbwebinars

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This research is oriented towards exploring mode-wise corridor level travel-time estimation using Machine learning techniques such as Artificial Neural Network (ANN) and Support Vector Machine (SVM). Authors have considered buses (equipped with in-vehicle GPS) as the probe vehicles and attempted to calculate the travel-time of other modes such as cars along a stretch of arterial roads. The proposed study considers various influential factors that affect travel time such as road geometry, traffic parameters, location information from the GPS receiver and other spatiotemporal parameters that affect the travel-time. The study used a segment modeling method for segregating the data based on identified bus stop locations. A k-fold cross-validation technique was used for determining the optimum model parameters to be used in the ANN and SVM models. The developed models were tested on a study corridor of 59.48 km stretch in Mumbai, India. The data for this study were collected for a period of five days (Monday-Friday) during the morning peak period (from 8.00 am to 11.00 am). Evaluation scores such as MAPE (mean absolute percentage error), MAD (mean absolute deviation) and RMSE (root mean square error) were used for testing the performance of the models. The MAPE values for ANN and SVM models are 11.65 and 10.78 respectively. The developed model is further statistically validated using the Kolmogorov-Smirnov test. The results obtained from these tests proved that the proposed model is statistically valid.

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System Verilog (Tutorial -- 2X1 Multiplexer)

1. A 2 X 1 M U LT I P L E X E R S Y S T E M V E R I L O G

2. S Y S T E M V E R I L O G A 2 X 1 M U LT I P L E X E R This Tutorial covers: logic — four-state integer type where the four possible states are: • 1 (high; True); • 0 (low; False; • x (unknown) — this means that the state is unknown; Verilog initializes four-state types to X. • z (high impedance) — this means that the state is disconnected and is essentially “floating.” output, input — describe the ports associated with a module and provides a way to communicate with a module assign — continuous assignment statement in system verilog module — for simulation of digital circuits in software and synthesis of digital circuits in hardware

3. S Y S T E M V E R I L O G A 2 X 1 M U LT I P L E X E R module mux2_1(out, i0, i1, sel); output logic out; input logic i0, i1, sel; assign out = (i1 & sel) | (i0 & ~sel); endmodule Creates a block of code which can be instantiated (i.e. used) as many times as needed in highboy other files in a design. This module is named mux2_1 and has four ports (out, i0, i1, sel) which allow other modules to communicate with it.

4. S Y S T E M V E R I L O G A 2 X 1 M U LT I P L E X E R module mux2_1(out, i0, i1, sel); output logic out; input logic i0, i1, sel; assign out = (i1 & sel) | (i0 & ~sel); endmodule out is an output of the module mux2_1. out is of the variable type logic and can have four possible values: z, x, 0, or 1 i0, i1, sel1 are inputs to the module mux2_1. These three inputs are also of the variable type logic and can have four possible values: z, x, 0, or 1

5. S Y S T E M V E R I L O G A 2 X 1 M U LT I P L E X E R module mux2_1(out, i0, i1, sel); output logic out; input logic i0, i1, sel; assign out = (i1 & sel) | (i0 & ~sel); endmodule assigns out the value of (i1*sel) + (i0*sel’) where * or & indicates AND; + or | indicates OR; ’ (~) indicates NOT (INVERT)

6. S Y S T E M V E R I L O G A 2 X 1 M U LT I P L E X E R module mux2_1_testbench(); logic i0, i1, sel; logic out; mux2_1 dut (.out, .i0, .i1, .sel); initial begin sel=0; i0=0; i1=0; #10; sel=0; i0=0; i1=1; #10; sel=0; i0=1; i1=0; #10; sel=0; i0=1; i1=1; #10; sel=1; i0=0; i1=0; #10; sel=1; i0=0; i1=1; #10; sel=1; i0=1; i1=0; #10; sel=1; i0=1; i1=1; #10; end endmodule Creates variables i0, i1, sel, and out of variable type logic Creates a block of code that can be used to simulate another module (in this case, mux2_1_testbench() will simulate the mux2_1 created on the preceding slides) Sets up the mux2_1 for testing/simulating and names it dut.

7. S Y S T E M V E R I L O G A 2 X 1 M U LT I P L E X E R module mux2_1_testbench(); logic i0, i1, sel; logic out; mux2_1 dut (.out, .i0, .i1, .sel); initial begin sel=0; i0=0; i1=0; #10; sel=0; i0=0; i1=1; #10; sel=0; i0=1; i1=0; #10; sel=0; i0=1; i1=1; #10; sel=1; i0=0; i1=0; #10; sel=1; i0=0; i1=1; #10; sel=1; i0=1; i1=0; #10; sel=1; i0=1; i1=1; #10; end endmodule At time = 0: sel i0 i1 = 000 At time = 10 time units: sel i0 i1 = 001 At time = 20 time units: sel i0 i1 = 010 And so on…. This block of code assigns binary values to the three inputs of dut: i0, i1, sel; i0, i1, sel are defined as inputs in the mux2_1 module shown on the preceding slides.

8. S Y S T E M V E R I L O G A 2 X 1 M U LT I P L E X E R In this introductory tutorial, we have created a 2X1 multiplexer in System Verilog and created a testbench to simulate all possible input combinations in ModelSim. out i0 i1 sel Click here for More Tutorials on Digital Logic & Circuits

System Verilog (Tutorial -- 2X1 Multiplexer)

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