Paper-review: A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives

Sep 15, 20152 likes631 views

Laboratory of Dependable Systems(I), GIEE, NTU

- Author: Kuan-Yu Liao, Chia-Yuan Chang, and James Chien-Mo Li, National Taiwan University - Publication: IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 2011

National Taiwan UniversityNational Taiwan University
A Parallel Test Pattern
Generation Algorithm to Meet
Multiple Quality Objectives
K.Y. Liao, IEEE Trans. Comput.-Aided Design
Intergr. Circuits Syst., Vol. 30, Issue 11
1
J.Y. Chen, 2015/09/15

Outline
• Introduction
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
2

Outline
• Introduction
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
3

Outline
• Introduction
– Background knowledge
– PODEM Quick Review
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
4

Introduction - Background Knowledge
• Single stuck-at fault (SSF) model is no longer
effective enough in deep sub-micron (DSM)
circuits
• Several quality metrics are introduced to grade
patterns
5

Introduction - Background Knowledge
• Quality metrics
– N-detect
– Physical-aware N-detect (PAN)
– Gate exhaustive (GE)
– Bridging coverage Estimate (BCE)
6

Introduction - Background Knowledge
• To achieve high quality test pattern generation (TPG),
quality objective are introduced during the process
• Additional quality objectives may cause lots of
backtracks during TPG
• Some tries to grade and select patterns from large-N-
detect test set generated by traditional TPG tool
• SWK adopted bit-wise parallel strategy to realize search-
space parallelism, thus get more chance to justify
additional quality objectives
7

Introduction - PODEM Quick Review
• Path-sensitizing ATPG algorithm
• After fault activation, system choose a gate from
D-frontier and then gradually map corresponding
D-drive objective to a PI/PPI decision, called
backtrace
• After each decision make, run implication to
update the logic value of circuit
• Heuristics such as X-path search are adopted
for early avoidance of backtrack
8

Outline
• Introduction
– Background knowledge
– PODEM Quick Review
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
9

Outline
• Introduction
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
10

Outline
• Introduction
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
11

Outline
• Introduction
• Split-into-W-Clones(SWK)
– 7-Valued Logic
– System Flow
• Experiment Result
• Conclusion
12

Outline
• Introduction
• Split-into-W-Clones(SWK)
– 7-Valued Logic
– System Flow
• Experiment Result
• Conclusion
19

Outline
• Introduction
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
20

Outline
• Introduction
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
21

Outline
• Introduction
• Split-into-W-Clones(SWK)
• Experiment Result
• Conclusion
24

Conclusion
• SWK optimize test pattern quality during TPG
• Might able to integrate SWK into other
parallelism strategy
• Word size are predefined and less flexible
• Only support parallel pattern generation target
on single fault
25

The document discusses various ATPG (Automatic Test Pattern Generation) methods and algorithms. It provides an introduction to ATPG, explaining that ATPG generates test patterns to detect faults in circuits. It then covers major ATPG classifications like pseudorandom, ad-hoc, and algorithmic. Several algorithmic ATPG methods are described, including the D-algorithm, PODEM, FAN, and genetic algorithms. Sequential ATPG is more complex due to memory elements. The summary reiterates that testing large circuits is difficult and many ATPG methods have been developed for combinational and sequential circuits.

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Paper-review: A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives

1. National Taiwan UniversityNational Taiwan University A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives K.Y. Liao, IEEE Trans. Comput.-Aided Design Intergr. Circuits Syst., Vol. 30, Issue 11 1 J.Y. Chen, 2015/09/15

2. Outline • Introduction • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 2

3. Outline • Introduction • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 3

4. Outline • Introduction – Background knowledge – PODEM Quick Review • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 4

5. Introduction - Background Knowledge • Single stuck-at fault (SSF) model is no longer effective enough in deep sub-micron (DSM) circuits • Several quality metrics are introduced to grade patterns 5

6. Introduction - Background Knowledge • Quality metrics – N-detect – Physical-aware N-detect (PAN) – Gate exhaustive (GE) – Bridging coverage Estimate (BCE) 6

7. Introduction - Background Knowledge • To achieve high quality test pattern generation (TPG), quality objective are introduced during the process • Additional quality objectives may cause lots of backtracks during TPG • Some tries to grade and select patterns from large-N- detect test set generated by traditional TPG tool • SWK adopted bit-wise parallel strategy to realize search- space parallelism, thus get more chance to justify additional quality objectives 7

8. Introduction - PODEM Quick Review • Path-sensitizing ATPG algorithm • After fault activation, system choose a gate from D-frontier and then gradually map corresponding D-drive objective to a PI/PPI decision, called backtrace • After each decision make, run implication to update the logic value of circuit • Heuristics such as X-path search are adopted for early avoidance of backtrack 8

9. Outline • Introduction – Background knowledge – PODEM Quick Review • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 9

10. Outline • Introduction • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 10

11. Outline • Introduction • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 11

12. Outline • Introduction • Split-into-W-Clones(SWK) – 7-Valued Logic – System Flow • Experiment Result • Conclusion 12

13. SWK - 7-Valued Logic 13

14. SWK - 7-Valued Logic 14

15. SWK - System Flow 15

16. SWK - System Flow 16

17. SWK - System Flow 17

18. SWK - System Flow 18

19. Outline • Introduction • Split-into-W-Clones(SWK) – 7-Valued Logic – System Flow • Experiment Result • Conclusion 19

20. Outline • Introduction • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 20

21. Outline • Introduction • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 21

22. Experiment Result 22

23. Experiment Result 23

24. Outline • Introduction • Split-into-W-Clones(SWK) • Experiment Result • Conclusion 24

25. Conclusion • SWK optimize test pattern quality during TPG • Might able to integrate SWK into other parallelism strategy • Word size are predefined and less flexible • Only support parallel pattern generation target on single fault 25

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