module 2-1 Design Analysis & Investigation of combinational logic in HDL.pptx

Digital System Design
Learning Module 2.1
Combinational Circuit Design

Analysis Vs Design Vs Investigation
Analysis: Analysis is a Greek word that equates to decomposition: "breaking a whole into its component parts (in
order to better understand it)".
Analysis of a problem:
Analysis of a problem is understanding the problem you're trying to solve. What environment is it in. Who are your
customers going be. What behaviors should your solution exhibit. etc
Analysis of a system:
System analysis can be defined as a deep decomposition of the structure or a module that has been designed before
to seek maximum information.
Design (Synthesis):
• System design means to make any module or a part of the structure from scratch and build it completely without
estimation.
• Design emphasizes a conceptual solution that fulfills the requirements, rather than its implementation
Investigation:
The process of inquiring into or following up; research; study; inquiry, especially patient or thorough inquiry or
examination; as, the investigations of the philosopher and the mathematician; the investigations of the judge, the
moralist. (making a judgement on the basis of information)
Technically leads to
• Verification
• Bug Finding

Analysis of Combinational Circuits
• The analysis of a combinational circuit requires that we determine the
function that the circuit implements. This task starts with a given logic
diagram and culminates with a set of Boolean functions, a truth table,
or, possibly, an explanation of the circuit operation
• The analysis can be performed manually by finding the Boolean
functions or truth table or by using a computer simulation program.
• The first step in the analysis is to make sure that the given circuit is
combinational and not sequential. The diagram of a combinational
circuit has logic gates with no feedback paths or memory elements .

To obtain the output Boolean functions from a logic diagram, we proceed as
follows:
1. Label all gate outputs that are a function of input variables with arbitrary
symbols—but with meaningful names. Determine the Boolean functions for
each gate output.
2. Label the gates that are a function of input variables and previously
labeled gates
with other arbitrary symbols. Find the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.
4. By repeated substitution of previously defined functions, obtain the
output Boolean functions in terms of input variables.

Example
Write the Boolean Function
What Does this mean?

Be Investigative!
What this circuit performs ?

Design of Combinational Circuits
The design of combinational circuits starts from the specification of the design
objective and culminates in a logic circuit diagram or a set of Boolean functions
from which the logic diagram can be obtained.
The procedure involves the following steps:
1. From the specifications of the circuit, determine the required number of inputs
and outputs and assign a symbol to each.
2. Derive the truth table that defines the required relationship between inputs
3. Obtain the simplified Boolean functions for each output as a function of the input
variables.
4. Draw the logic diagram and verify the correctness of the design (manually or by
simulation).

Design Example
• Develop a BCD to Excess 3 Coder

Design Example: Excess-3 Coder

Design of Full Adder
Design of Full Adder

Four Bit Adder Design
What is the performance concern here?

Design of a Multiplier 2 bit by 2bit

Design A Magnitude Comparator
For Equality
For A>B Observe the relative bits,
starting from MSB
1- if A3 =1 and B3=0, A>B finish
(A3 B’3)
2- if A2=1 and B3=0, A>B finish
(X3 A2 B’2)
3- if A1 =1 and B1=0, A>B finish
(X3 X2 A1 B’1)
4-if A0 =1 and B0=0, A>B finish
(X3 X2 X1 A0 B’0)

Three to Eight Line Decoder
Home Work for Implementation

Designs of Adder using decoders

Design a Decoder
Diagram for Decoder is your
task.

2x1 Multiplexer
4x1 Multiplexer

Implementation of Boolean Function using Multiplexer
Develop Truth Table
Try the Implementation of
Using multiplexer

HDL Models for combinational Logic
• Gate Level Models ( Schematic oriented)
• Data Flow Models ( assigning the values to variable as if they are
registers)
• Behavioral Models ( following the procedure of logic circuit)

Data Flow Model
• Using binary / logical operators to get results in the binary
• Using “assign” keyword for continuous assignment

Behavioral Model:
• Usually describe the circuits in form of algorithmic level.
• Well Suited for sequential circuits
• Keyword “always”
HDL Example 4.6
Specific to
behavioral
When ever any of
Them changes
Subsequent instructions execute

module 2-1 Design Analysis & Investigation of combinational logic in HDL.pptx

Test Bench ~ providing Stimulus to HDL
Module
• “initial” – executes once at time t=0, follows the instructions in the
‘initial’ block
• Generating a set of values in test bench

Association of variables in test bench and
module

Test Bench ~ Results Display
• Wave forms (Timing Diagrams)
• Text on screen
Syntax Example
$display ("[$display] time=%0d A=%b B=0x%0h", $time, A, B);
Time = 3 A= 10 B=0x2d
Avoids leading digits

Test Bench ~ Results Display
The $write and the $display tasks work in the same way, and the only
difference is that the $display task adds a new line character at the end
of the output, while the $write task does not.
module tb;
initial begin
$display ("This ends with a new line ");
$write ("This does not,");
$write ("like this. To start new line, use newline char");
$display ("This always starts on a new line!");
end
endmodule
This ends with a new line
This does not, like this. To start a new line, use newline char

Inputs and outputs are declared as reg and wire
‘Initial’ looking for simulation time
Stimulus generation / same time =0
Output of the test bench
Module definition of 2x1 Multiplexer

Types of Verifications
• Functional Verification
What is the output in response to inputs
• Timing Verification
How output appear as the inputs change with reference to time
3
4
5
6
7 8
9
2
1

Test bench
A B C
+
‘Monitor’
Prints the text whenever
Signal changes

module 2-1 Design Analysis & Investigation of combinational logic in HDL.pptx

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