IO INTERFACING in unit 2 8086 Microprocessor

8255-Programmable Peripheral Interface
Implement the parallel data transfer between processor and slow peripheral
devices
ADC,DAC,KEYBOARD,7-SEGMENT DISPLAY,LCD…
8255-Three ports: Port-A, Port-B, Port-C
8255- Three Modes: Mode 0, mode 1, mode 2
Mode 0- Simple I/O port
Mode 1- Handshake I/O port
Mode 2- Bidirectional I/O port
Port A: programmed  any one of the three modes
Port B: programmed  Work Either mode 0 or mode 1
Port C: Pins (8 Pins)  different assignments  depends on mode of Port
A and B.

If Port- A and B  programmed in Mode 0
Port C will be
1. 8 bit parallel port in mode 0 for i/p or o/p
2. Two 4-bit parallel port in mode 0 for i/p or o/p
3. Individual pins  can set or reset for various control applications
If Port- A  programmed in Mode 1 /mode 2 and Port B
programmed in Mode 1
Port C will be
Some pins  used Handshake Signals
Remaining pins  i/pp and o/p

I/O MODES OF 8255
MODE-1 MODE-2 MODE-3
All the three ports 
Programmed either I/P or
O/P
Only ports A and B
O/P
Only ports A 
O/P
O/Ps  Latched O/Ps  Latched -
I/Ps Not Latched I/Ps  Latched -
Do not have handshake or
interrupt capability
Having handshake or
Having handshake or
Port C pins  used as
handshake signals
5 Pins of Port C pins 
used as handshake signals
Handshake signals  exchanged between processor
and peripherals
Ports in mode-0  used to
interface DIP switches,
Hexa keyboard, LEDS ,7
segment to the processor.
Interrupt driven data
transfer scheme is possible
Data transfer between 2
computers or floppy disk

Programming (or Initializing) 8255
8255 –Two Control Words
1. I/O mode set Control word (MSW) specify the I/O functions
2. Bit set/reset (BSR) Control word.  Set/ reset the individual pins of
port C

Serial Data Communication
1.Fastest way to transmitting data  Parallel Data Transfer
2. Long Distance  Parallel data transfer  Too many Wires
3. Parallel serial conversion needed
Three terms:
1. Simplex  Transmit data can only on direction.
2. Half dulpex either direction between two system.
3. Full duplex send and receive data at same time.
Serial data can sent 1. Synchronously 2. asynchronously
Synchronous transmission:
Constant rate
Start and end block are identified with specific bytes or bit patterns.
2. Asynchronous Transmission
Data transmit one by one
Each data can identifiy its start and 1 or 2 bits which identify its send.
Baud rate =1/ the time for a bit sent.

INTEL 8251A(USART)
INTEL 8251A Universal Synchronous asynchronous receiver
transmitter
INTEL 8250 UART Universal asynchronous receiver
transmitter
Blocks:
1. Read/Write control logic, 2.Transmitter, 3. Receiver, 4.Modem
control
Read/write Control Logic:
Three register:1.contol reg, 2.status reg, 3. bata buffer

CS: It is chip select.
low signal  processor has selected 8251 in order to communicate with
the peripheral devices.
C/D’: As the system has control, status and data register.
high signal  control or status register is addressed.
low signal data register is addressed.
RD’ and WR’: Both read and write are active low signal pins.
CLK and RESET:
CLK stands for clock and it produces the internal timing for the device.
high signal at the RESET pin puts the 8251 in the idle mode.

Transmit Buffer
This unit is used to change the parallel data received from the CPU into
serial data by inserting the necessary framing information.
Once the data is transformed into serial form, then in order to transmit it to the
external devices, it is provided to the TxD pin of the 8251.
Buffer register: Basically the data provided by the processor is stored in the
buffer register. As we know that initially, the CPU provides parallel data to
8251. So, the processor loads the parallel data to the buffer register. Further, this
data is fed to the output register.
Output register: The parallel data from the buffer register is fed to the empty
output register. This register changes the 8-bit parallel data into a stream of
serial bits. Then further the serial data is provided at the TxD pin so as to have
its transfer to the peripheral device.

If buffer register empty TxRDYhigh
If output register empty TxEXPTYhigh
TxC: It stands for transmitter clock and is an active low pin. It controls the rate of
character transmission by the USART.
Receive Buffer
This unit takes the serial data from the external devices, changes the serial data into
the parallel form so that it can be accepted by the processor.
It consists of 2 registers: 1. receiver input register 2. buffer register.
RxD  Normally high….
When RxD line goes Low Control logic Assumes—>Start Bit….
Wait for Half bit time….and Samples Again….
If still low  then the receive accept the character and load it into buffer register.
CPU reads the Parallel data from the buffer register.
Then RxRDY signal high…this signal used as interuppt or status to indicate the
readiness of receiver.

RxC’  is used to control the rate of received bits.
During  asynchronous mode  SYNDET/BRKDET
Will indicate the intentional break in the transmission
If RxD  low more than 2 character times then asserted as high  to indicate the
break in the transmission.
During  synchronous mode  SYNDET/BRKDET
Will indicate the reception of the synchronous character.
if high in SYNDET.

8279
KEYBOARD /DISPLAY
CONTROLLER

It relieves the processor from the time consuming task like keyboard
scanning and display refreshing.
Features
1. It provides a scanned interface to a 64-contact key matrix, with two more
keys CONTROL and SHIFT.
2. It provides three input modes for keyboard interface;
Scanned Keyboard Mode
Scanned Sensor Matrix Mode
Strobed Input Mode
3. It has built-in hardware to provide key debounce.
4. It allows key depressions in 2 key lockout or N-key rollover mode
5. Features of Intel 8279 provides 8 byte FIFO RAM to store keycodes. This
allows to store 8 key board inputs when CPU is busy in performing his own
computation.
6. It provides multiplexed display interface with blanking and inhibit
options.
7. It provides 16 byte display RAM to store display codes for 16 digits,
allowing to interface 16 digits.
8. In auto increment mode, address of display RAM and FIFO RAM is
incremented automatically which eliminates extra command after each
read/write operation to access successive locations of display RAM and
FIFO

9. Features of Intel 8279 provides two output modes for display
interface.
Left Entry (typewriter type)
Right Entry (calculator type)
10. Simultaneous keyboard and display operation facility allows to
interleave keyboard and display software
Interrupt mode, the processor is requested service only if any
key is pressed, otherwise the CPU will continue with its main task.
In the Polled mode, the CPU periodically reads an internal flag of
8279 to check whether any key is pressed or not with key
pressure.
•Scanned Keyboard Mode In this mode, the
− key matrix can be
interfaced using either encoded or decoded scans. In the encoded scan,
an 8×8 keyboard or in the decoded scan, a 4×8 keyboard can be
interfaced. The code of key pressed with SHIFT and CONTROL status is
stored into the FIFO RAM.
•Scanned Sensor Matrix In this mode, a
− sensor array can be
interfaced with the processor using either encoder or decoder scans. In
the encoder scan, 8×8 sensor matrix or with decoder scan 4×8 sensor
matrix can be interfaced.
•Strobed Input In this mode, when the control line is set to 0, the
−
data on the return lines is stored in the FIFO byte by byte.

Keycode entry in FIFO for scan keyboard mode

8259
PROGRAMMABLE
INTERRUPT
CONTROLLER (PIC)

Features of 8259 PIC microprocessor –
Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
It can be programmed either in level triggered or in edge triggered
interrupt level.
We can masked individual bits of interrupt request register.
We can increase interrupt handling capability upto 64 interrupt level
by cascading further 8259 PIC.
Clock cycle is not required.

Data Transfer between Memory to I/O device or I/O device to Memory
through only Microprocessor.
• Data transferred from memory to I/O devices
1. Processor sends address and control signals to read the data from
memory
2. The processor send address and control signals to I/O devices to write
data to I/O devices.
• Similarly I/O devices to memory.
In above method data transferred between memory and I/O devices
Can’t directly. Even they are connected in common bus.
Can’t select simultaneously select two devices.
So that we go for DMA.
I/O device can access directly with memory.
It will transfer a large amount of data.
Some DMA controller will perform memory to memory transfer.

• DMA controller has one channel which serves for one devices.
• Actual DMA controller have  more than one channel.it will service
independently
• Each channel address register , control register and count register.
• DMA controller  work with slave or master mode.
• In slave mode
1. Microprocessor  Loads the address reg. with starting address of the
memory
2.Loads the count register with no. of bytes to be transferred and loads
the control register with control information
Performing DMA operation Processor has to initialize or program the I/O
device and DMA controller.

Consider bulk of data transfer from floppy to memory.
1. Processor initializes both  DMA controller and Floppy controller.
2. DMA controller informed about address, type of DMA, No. of bytes to
be transferred
3. Floppy controller is informed to go for a DMA.
4. When I/O devices needs a DMA transfer it sends a DMA request signal
to the DMA controller.
5. When DMA controller receives a DMA request, it sends a HOLD request
to the processor.
6. At the end of current instruction execution  the processer relives all
bus activity , data and control pins to high impedance state.
7. Then the processor send an ACK (HLDA) signal to DMA controller.
8. When controller receives the ACK signal its takes control of the
system bus and begins to work as master.
9. DMA controller  DMA ack signal to I/O devices .the DACK signal will
inform the devices to get ready for DMA transfer.

READ operation
1. DMA controller  output the memory address on address bus.
2. Asserts MEMR’ & IOW’
3. DMA reading Memory Location
4. The memory output the data bus & this data will be written into I/O
port.
Write operation
1.DMA controller output the memory address on the address bus.
2. Asserts MEMW’ & IOR’ signals.
3. DMA write refer to writing data to memory
4. I/O devices output the data on the data bus and this data will be
written into memory.
When the data transfer is complete the DMA controller un-asserts its
HOLD request signal to the processor and the processor take control of
the system bus.

DMA  Developed 8085/8086/8088
High speed data transfer between memory and I/O device.
4 –channels
So 4 I/O devices
It can not connected in cascade like 8237
Each channel  Address reg. & count reg.  Store the memory
address and Count Value for no. of byte to be read/write by DMA
respectively
Also mode Set Reg. and Status Reg.
40 pin IC
Each Channel  independently programmable to transfer upto 64Kb.

Pin Details
1. CLK 5 MHz
2. CS’  Select the 8257 Programming mode.
3. Reset high  All internal Register to be Cleared.
4. Ready  Low 8257 enter wait State
5. HRQ Hold request output Signal(8257 to Processor HOLD pin)
6. HLDA HOLD ack Signal. Processor Acceptance ACK
7. DREQ3 to DREQ0DMA request input (4 Channel i/Ps)
8. DACK3 to DACK0 DMA ACK O/P signals.
9. D0-D7 Data bus line(used to Data transfer)
10.IoR’ Bidirectional I/O read Control Signal.
11.IoW’ Bidirectional I/O write Control Signal.
12.TC  Terminal Count
13.MARK Modulo -128 Mark
14.A3 to A0 4 bidirectional address line
15.A7 to A4  Unidirectional Address line
16.AEN Address enable output signal.
17.ADSTB Address strobe output signal.
18.MEMR’ Memory Read Control
19.MEMW’ memory write control signal.

IO INTERFACING in unit 2 8086 Microprocessor

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IO INTERFACING in unit 2 8086 Microprocessor