Digital System Design-Switchlevel and Behavioural Modeling

MATRUSRI ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
SUBJECT NAME: DIGITAL SYSTEM DESIGN WITH VERILOG
FACULTY NAME: Mrs. B. Indira Priyadarshini
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INTRODUCTION:
Verilog provides the ability to design at a MOS-transistor level. Design at this
level is rare with the increasing complexity of circuits and with the availability
of sophisticated CAD tools. Behavioral modeling represents the circuit at a very
high level of abstraction. Design at this level resembles C programming more
than it resembles digital design. Verilog is rich in behavioral constructs that
provide the designer with a great amount of flexibility.
UNIT-II
OUTCOMES:
After successful completion of this Unit students should be able to
Understand modeling of bidirectional pass switches and behaviour of the
digital circuit design.
Explain the method to specify delays.
Build basic switch-level circuits and algorithmic level in Verilog, using
available switches.
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CONTENTS:
Switch-Modeling Elements
Delay Specification on Switches
Examples
OUTCOMES:
Students will be able to build basic switch-level circuits in Verilog, using
available switches.
MODULE-I: Switch-Level Modeling
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 Modeling transistor networks at the switch-level more accurately
represents their operation.
 Verilog provides unidirectional and bidirectional primitives that you can
use to model the switch networks.
 The following are unidirectional primitives:
cmos nmos pmos pullup
rcmos rnmos rpmos pulldown
 The following are bidirectional primitives:
tran tranif0 tranif1
rtran rtranif0 rtranif1
Verilog Switch Primitives
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Source
Gate
Drain
pmos(drain,source,gate);
Source
Gate
Drain
nmos(drain,source,gate);
Source
Drain
pgate
ngate
cmos (drain, source, ngate, pgate)
data1 data2
control
tranif1 (data1, data2, control);
tranif0 (data1, data2, control);

 The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed
when transistor-level circuits are designed.
 Power and ground sources are defined with keywords supply1 and supply0.
supply1 vdd;
supply0 gnd;
assign a = vdd; //Connect a to vdd
assign b = gnd; //Connect b to gnd
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 Resistive switches devices have a high source-to-drain impedance.
Regular switches have a low source-to-drain impedance.
 Resistive switches reduce signal strengths when signals pass through them.
Regular switches retain strength levels of signals from input to output.
rnmos rpmos //resistive nrnos and pmos switches
rcmos //resistive cmos switch
rtran rtranif0 rtranifl //resistive bidirectional switches

Delay Specification on Switches
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Switch
Element
Delay Specification Examples
Delay specification on MOS and CMOS Switches
pmos, nmos,
rpmos, rnmos
Zero (no delay)
One (same delay on all
transitions)
Two (rise, fall)
Three (rise, fall, turnoff)
pmos p1(out, data, control);
pmos #(1) p1(out, data, control);
nmos #(1, 2) p2(out, data, control);
nmos #(1, 3, 2) p2(out, data, control);
cmos, rcmos Zero, one, two or three
delays (same as above)
cmos #(5) c2(out, data, nctrl, pctrl);
cmos #(1,2) c1(out, data, nctrl, pctrl);
Delay specification for Bidirectional Switches
tran, rtran No delay specification
allowed
tranif1,
rtranif1
tranif0,
rtranif0
Zero (no delay)
One (both turn-on and
turn-off)
Two (turn-on, turn-off)
rtranif0 rt1(inout1, inout2, control);
tranif0 #(3) T(inout1, inout2, control);
tranif1 #(1,2) t1(inout1, inout2, control);

Examples
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module my-nor (out, a, b) ;
output out;
input a, b;
//internal wires
wire c;
//set up power and ground lines
supply1 pwr; //pwr is connected to Vdd
supply0 gnd ; //gnd is connected to Vss
//instantiate pmos switches
pmos (c, pwr, b);
pmos (out, c, a);
//instantiate nmos switches
nmos (out, gnd, a);
nmos (out, gnd, b);
endmodule

//stimulus to test the gate The output of the simulation:
module stimulus;
reg A, B;
wire OUT;
//instantiate the my-nor module
my-nor n1(OUT, A, B);
//Apply stimulus
initial
begin
//test all possible combinations
A = 1’b0; B = 1’b0;
#5 A = 1’b0; B = 1’b1;
#5 A = 1’b1; B = 1’b0;
#5 A = 1’b1; B = 1’b1;
end
//check results
initial
$monitor($time, " OUT = %b, A = %b, B = %b", OUT, A, B);
endmodule
Examples
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Examples
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module my-mux (out, S, i0, i1);
output out;
input S, i0, i1;
//internal wire
wire sbar;
//complement of S
//use my-nor defined previously.
my-nor nt(sbar, S, S);
//equivalent to a not gate
//instantiate cmos switches
cmos (out, i0, sbar, S);
cmos (out, i1, S, sbar);
endmodule

1. The switch level model can be used in the simulation of the transistors.
2. The switch level of modeling provides a level of abstraction between the
logic and analog-transistor levels of abstraction.
3. Switches are unidirectional or bidirectional and resistive or non-resistive
for each group.
4. Resistive switches reduce signal strengths when signals pass through
them.
5. Regular switches retain strength levels of signals from input to output.
Questions & Answers
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CONTENTS:
Structured Procedures
Procedural Assignments
OUTCOMES:
Students will be able to
•Understand the significance of structured procedures and procedural
assignments.
•Use behavioral modeling statements in practical examples.
MODULE-II: Behavioral Modeling
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Two basic structured procedure statements
 always
 initial
o All behavioral statements can appear only inside these blocks
o Each always or initial block has a separate activity flow (concurrency)
o Start from simulation time 0
o Cannot be nested
o Multiple blocks, execute in parallel
• All start at time 0
• Each finishes independently
Initial block
 Executes only once during a
simulation
 Syntax:
initial
begin
// behavioral statements
end
Always block
 Execute the statements in a
looping fashion
 Syntax:
always
begin
// behavioral statements
end

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Initial block Example:
module stimulus;
reg x, y, a, b, m;
initial
m= 1’b0;
initial
begin
#5 a=1’b1;
#25 b=1’b0;
end
initial
begin
#10 x=1’b0;
#25 y=1’b1;
end
initial
#50 $finish;
endmodule
Always block Example:
module clock_gen;
reg clock;
// Initialize clock at time zero
initial
clock = 1’b0;
// Toggle clock every half-cycle
//(time period =20)
always
#10 clock = ~clock;
initial
#1000 $finish;
endmodule

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 Assignments inside initial and always
 Are used to update values of reg, integer, real, or time variables
• The value remains unchanged until another procedural assignment
updates it
Syntax
<lvalue> = <expression>
• <lvalue> can be
o reg, integer, real, time
o A bit-select of the above (e.g., addr[0])
o A part-select of the above (e.g., addr[31:16])
o A concatenation of any of the above
• <expression> is the same as introduced in dataflow modeling
• What happens if the widths do not match?
o LHS wider than RHS => RHS is zero-extended
o RHS wider than LHS => RHS is truncated (Least significant part is
kept)

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The two types of procedural assignments
• Blocking assignments
• Non-blocking assignments
Blocking assignments are executed in order (sequentially)
Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1;
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
end
All executed at time 0
executed at time 15

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Non-blocking assignment: The next statements are not blocked for this one
Syntax:
<lvalue> <= <expression>
Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1;
reg_b[15:13] <= #10 {x, y, z};
count <= count + 1;
end
Scheduled to run at time 15
Scheduled to run at time 10

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Application of non-blocking assignments
• Used to model concurrent data transfers
Example:
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1;
end
Race condition
When the final result of simulating two (or more) concurrent processes
depends on their order of execution
Example:
b = a;
a = b;
Solution:
b <= a;
a <= b;
The old value of reg1 is used
begin
temp_b = b;
temp_a = a;
b = temp_a;
a = temp_b;
end

1. In non-blocking assignment, the compiler evaluates all RHS for the
current time unit and assign to LHS at the end of the time unit.
2. All behavioral statements are appear only inside structured procedure
statements.
3. The statements always and initial cannot be nested.
4. The statements in the always block executes in a looping fashion.
5. A blocking assignment will not block execution of statements tat follow in
a parallel block.
Questions & Answers
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CONTENTS:
Delay-based Timing Control
Event-based Timing Control
Level-sensitive Timing Control
OUTCOMES:
Students will be able to understands and describe timing control mechanism in
behavioral modeling.
MODULE-III: Timing Control
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No timing controls  No advance in simulation time
Three methods of timing control
•delay-based
•event-based
•level-sensitive
Delay  Duration between encountering and executing a statement
Delay symbol: #
Delay specification syntax:
<delay>
::= #<NUMBER>
||= #<identifier>
||= #<mintypmax_exp> <,<mintypmax_exp>>*)
Types of delay-based timing controls
1. Regular delay control
2. Intra-assignment delay control
3. Zero-delay control

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Symbol: non-zero delay before a procedural assignment
//define parameters
parameter latency = 20;
parameter delta = 2;
//define register variables
reg x, y, z, p, q;
initial
begin
x = 0; // no delay control y control with a number.
#10y = 1;//Delay execution of y = 1 by 10 units
#latency z = 0; // Delay control with identifier. Delay of 20units
#(latency + delta) p = 1; // Delay control with expression
#y x = x + 1; // Delay control with identifier. Take value of y.
#(4:5:6) q = 0; // Minimum, typical and maximum delay values.
end
Regular Delay Control

Intra-assignment Delay Control
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Symbol: non-zero delay to the right of the assignment operator
Operation sequence:
1. Compute the right-hand-side expression at the current time.
2. Defer the assignment of the above computed value to the LHS by the
specified delay.
reg x, y, z;
initial
begin
x = 0;
z = 0;
y = #5 x + z;
end
/*Take value of x and z at the
time=0, evaluate x + z and then wait
5 time units to assign value to y. */
initial
begin
x = 0;
z = 0;
temp_xz = x + z;
#5 y = temp_xz;
end
/* Even though x and z might change
between 0 and 5, the value assigned
to y at time 5 is unaffected*/

Zero-Delay Control
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initial
begin
x = 0;
y = 0;
end
initial
begin
#0 x = 1; //zero delay control
#0 y = 1;
end
Symbol: #0
Different initial/always blocks in the same simulation time
oExecution order non-deterministic
Zero-delay ensures execution after all other statements
oEliminates race conditions
Multiple zero-delay statements
oNon-deterministic execution order

Event-based Timing Control
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Event
•Change in the value of a register or net
•Used to trigger execution of a statement or block (reactive
behavior/reactivity)
Types of Event-based timing control
1. Regular event control
2. Named event control
3. Event OR control

Regular event control
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Symbol: @(<event>)
Events to specify:
oposedge sig: Change of sig from any value to 1or from 0 to any value
onegedge sig: Change of sig from any value to 0 or from 1 to any value
oSig: Any change in sig value
@(clock) q = d;
//q = d is executed whenever signal clock changes value
@(posedge clock) q = d;
/*q = d is executed whenever signal clock does a positive transition ( 0 to 1,x
or z, x to 1, z to 1 ) */
@(negedge clock) q = d;
/*q = d is executed whenever signal clock does a negative transition ( 1 to 0,x
or z, x to 0, z to 0) */
q = @(posedge clock) d;
//d is evaluated immediately and assigned to q at the positive edge of clock

Named event control
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Can declare (name) an event, and then trigger and recognize it.
oVerilog keyword for declaration: event
event calc_finished;
oVerilog symbol for triggering: ->
->calc_finished
oVerilog symbol for recognizing: @()
@(calc_finished)
// data buffer storing data after the last packet of data has arrived.
event received_data;
begin
if(last_data_packet)
->received_data;
end
always @(received_data)
data_buf = {data_pkt[0], data_pkt[1], data_pkt[2], data_pkt[2]};

Event OR control
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Used when need to trigger a block upon occurrence of any of a set of events.
The list of the events: sensitivity list
Verilog keyword: or
//A level-sensitive latch with asynchronous reset
always @( reset or clock or d) //Wait for reset or clock or d to change
begin
if (reset) //if reset signal is high, set q to 0.
q = 1'b0;
else
if(clock) //if clock is high, latch input
q = d;
end

Level-sensitive Control
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Verilog keyword: wait()
always
wait(count_enable)
#20 count=count+1;
Level-sensitive vs. event-based
event-based:
wait for triggering of an event
(change in signal value)
level-sensitive:
wait for a certain condition
(on values/levels of signals)

1. Regular delays defer the execution of the entire assignment.
2. Zero delay is used to eliminate race conditions.
3. An event is the change in the value on register or a net.
4. To trigger an event, @ operator is used.
5. The wait statement is level sensitive.
Questions & Answers
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CONTENTS:
Conditional Statements
Multiway Branching
Loops
OUTCOMES:
Students will be able to use behavioral modeling statements in practical
examples.
MODULE-IV: Statements and Loops
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Conditional Statements
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 Just the same as if-else in C
 Syntax:
if (<expression>) true_statement;
if (<expression>) true_statement;
else false_statement;
if (<expression>) true_statement1;
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;
 True is 1 or non-zero
 False is 0 or ambiguous (x or z)
 More than one statement: begin end

Examples
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if (number_queued < MAX_Q_DEPTH)
begin
data_queue = data;
number_queued = number_queued +1;
end
else $display(“Queue full! Try again.”);
if (alu_control==0)
y = x+z;
else if (alu_control==1)
y = x-z;
else if (alu_control==2)
y = x*z;
else
$display(“Invalid ALU control signal.”);
if (!lock) buffer = data;
if (enable) out = in;

Multiway Branching
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 Similar to switch-case statement in C
 Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase
 Notes:
• <expression> is compared to the alternatives in the order specified.
• Default statement is optional
 The case statements compares <expression> and alternatives bit-for-bit
• x and z values should match
 casex and casez keywords
• casez treats all z values as “don’t care”
• casex treats all x and z values as “don’t care”

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module Priorityencoder(encoding, next_state);
input [3:0] encoding;
output reg next_state;
always@(encoding)
begin
casex(encoding)
4’b1xxx: next_state=2’b11;
4’b01xx: next_state=2’b10;
4’b001x: next_state=2’b01;
4’b0001: next_state=2’b00;
default: next_state=2’b00;
endcase
end
endmodule
Examples

Loop
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 The while loop syntax:
while (<expression>)
statement;
 The for loop
•Similar to C
•Syntax
for( init_expr; cond_expr; change_expr)
statement;
 The repeat loop
•Syntax:
repeat( number_of_iterations )
statement;
•The number is evaluated only when the loop is first encountered
 The forever loop
•Syntax:
forever
statement;
•Equivalent to while(1)

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integer count;
initial
begin
count = 0;
while (count < 128)
begin
$display(“Count = %d”, count);
count = count + 1;
end
end
Examples
integer count;
initial
for( count=0;count<128;count=count+1);
$display(“Count=%d”,count);
integer count;
initial
begin
count = 0;
repeat (128)
begin
$display(“Count = %d”, count);
count = count + 1;
end
end
reg clock=1’b0;
initial
begin
forever #10 clock=~clock;
end

1. Condition statements are used for making decisions based upon certain
conditions.
2. Case statement is a shortcut to achieve the same result as if-else-if .
3. Forever executes until the $finish task is encountered.
4. Repeat construct executes the loop a fixed number of times.
5. While loop executes until the while expression becomes false.
Questions & Answers
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CONTENTS:
Sequential Block
Parallel Block
Special Features of Blocks
OUTCOMES:
Students will be able to understand the significance of blocks in behavioural
modeling.
MODULE-V: Sequential and Parallel blocks
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Blocks: used to group multiple statements
Sequential Blocks
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•Keywords: begin end
•Statements are processed in order.
A statement is executed only after its preceding one completes.
Exception: non-blocking assignments with intra-assignment delays
A delay or event is relative to the simulation time when the previous
statement completed execution
//without delay
reg x, y;
reg [1:0] z, w;
initial begin
x = 1'b0;
y = 1'b1;
z = {x, y};
w = {y, x};
end
//with delay
reg x, y;
reg [1:0] z, w;
initial begin
x = 1'b0;
#5 y = 1'b1;
#10 z = {x, y};
#20 w = {y, x};
end

Parallel Blocks
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•Keywords: fork, join
•Statements in the blocks are executed concurrently
•Timing controls specify the order of execution of the statements
•All delays are relative to the time the block was entered
oThe written order of statements is not important
//with delay
reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0;
#5 y = 1'b1;
#10 z = {x, y};
#20 w = {y, x};
join
//deliberate race condition
reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0;
y = 1'b1;
z = {x, y};
w = {y, x};
join

Nested blocks
•Sequential and parallel blocks can be mixed
initial
begin
x=1’b0;
fork
#5 y=1’b1;
#10 z={x,y};
join
#20 w={y,x};
end
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Named blocks
Syntax:
begin: <the_name> fork: <the_name>
… …
end join

Advantages:
Can have local variables
Are part of the design hierarchy.
Their local variables can be accessed using hierarchical names
Can be disabled
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module top;
…
initial
begin : block1
integer i; //hierarchical name: top.block1.i
…
end
initial
fork : block2
reg i; //hierarchical name: top.block2.i
…
join
endmodule

Disabling named blocks
•Keyword: disable
•Action: Similar to break in C/C++, but can disable any named block not
just the inner-most block.
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module find_true_bit;
reg [15:0] flag;
integer i;
initial begin
flag = 16'b 0010_0000_0000_0000;
i = 0;
begin: block1
while(i < 16)
begin
if (flag[i])
begin
$display("Encountered a TRUE bit at element number %d", i);
disable block1;
end // if
i = i + 1;
end // while
end // block1
end //initial
endmodule

1. Block statements are used to group multiple statements to act together as
one.
2. The statements inside Sequential block executes one after another.
3. Statements in a parallel block are executed concurrently.
4. Disable allows disabling of any named block in the design.
Questions & Answers
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CONTENTS:
Generate
Generate Loop
Generate Condition
Generate Case
OUTCOMES:
•Students will be able to understand the generate block.
MODULE-VI: Generate Block
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Generate statements allow Verilog code to be generated dynamically before
the simulation time begins.
This is particularly useful when same operation is to be performed for
multiple bits of vector.
All the instructions are coded within generate – endgenerate keywords.
Generated instantiations are one or more of the following types
oModules
oUser Defined Primitives
oVerilog Gate Primitives
oContinuous Assignments
oinitial and always blocks.
Generate
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Various data types allowed in a generate statement to support
interconnections between structural elements and/or procedural blocks.
onet, reg
ointeger, real, time, realtime,
oevent
Tasks and Functions are allowed within a Generate Scope, but not in a
generate loop.
Some module declarations and module items are not permitted in a generate
statement are
oparameter, local parameter
oinput, output and inout declarations
ospecify blocks.
Generate
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A generate loop allows one or more of the aforementioned to be instantiated
multiple times using a FOR loop.
Generate Loop.
In the above example, before the actual simulation, the code is elaborated to
create a flat representation without the generate block. The elaborated code is
simulated.
Thus generate blocks are a simply a convenient way of replacing multiple
repetitive Verilog blocks.
genvar is a keyword to declare a variable that is used only to evaluate the
generate block.
Its value can be defined only by the generate loop.
Two generate loops can be nested, provided they have different genvars.
Generate Loop
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There are three methods to create generate statements:
•Generate Loop
•Generate Condition
•Generate Case

/* This module generates a bit-
wise xor of two N-bit buses*/
module bitwise_xor (out, i0, i1);
parameter N = 32;
output [N-1:0] out;
input [N-1:0] i0, i1;
genvar j;
generate for (j=0; j<N; j=j+1)
begin: xor_loop
xor g1 (out[j], i0[j], i1[j]);
end
endgenerate
endmodule
Bitwise XOR
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/*As an alternate style, the xor gates
could be replaced by always blocks.*/
module bitwise_xor (out, i0, i1);
parameter N = 32;
output [N-1:0] out;
reg [N-1:0] out;
input [N-1:0] i0, i1;
genvar j;
generate for (j=0; j<N; j=j+1)
begin: bit
always @(i0[j] or i1[j])
out[j] = i0[j] ^ i1[j];
end
endgenerate
endmodule

module ripple(co, sum, a0, a1, ci);
parameter N = 4;
output [N-1:0] sum; output co;
input [N-1:0] a0, a1; input ci;
wire [N-1:0] carry;
assign carry[0] = ci;
genvar i;
generate
for (i=0; i<N; i=i+1)
begin: r_loop
wire t1, t2, t3;
xor g1 (t1, a0[i], a1[i]);
xor g2 (sum[i], t1, carry[i]);
and g3 (t2, a0[i], a1[i]);
and g4 (t3, t1, carry[i]);
or g5 (carry[i+1], t2, t3);
end
endgenerate
assign co = carry[N];
endmodule
Ripple Adder
MATRUSRI
ENGINEERING COLLEGE
For the generate loop, the relative
hierarchical instance names are:
xor :r_loop[0].g1, r_loop[1].g1,
r_loop[2].g1, r_loop[3].g1
r_loop[0].g2, r_loop[1].g2, r_loop[2].g2,
r_loop[3].g2
and :r_loop[0].g3, r_loop[1].g3,
r_loop[0].g4, r_loop[1].g4, r_loop[2].g4,
r_loop[3].g4
or :r_loop[0].g5, r_loop[1].g5,
Generated instances are connected with
the following generated nets
Nets: r_loop[0].t1, r_loop[0].t2,
r_loop[0].t3
r_loop[1].t1, r_loop[1].t2, r_loop[1].t3

// This module implements a parametrized multiplier
module multiplier (product, a0, a1);
parameter a0_width = 8; // 8-bit bus by default
parameter a1_width = 8; // 8-bit bus by default
localparam product_width = a0_width + a1_width;
output [product_width -1:0] product;
input [a0_width-1:0] a0;
input [a1_width-1:0] a1;
generate
if (a0_width <8) || (a1_width < 8)
cla_multiplier#(a0_width, a1_width) m0 (product, a0, a1);
else
tree_multiplier#(a0_width, a1_width) m0 (product, a0, a1);
endgenerate //end of the generate block
endmodule
Generate Condition
MATRUSRI
ENGINEERING COLLEGE
A generate conditional is just like an if-else-if.

// This module generates an N-bit adder
module adder(co, sum, a0, a1, ci);
parameter N = 4; // 4-bit bus by default
output [N-1:0] sum;
output co;
input [N-1:0] a0, a1;
input ci;
generate
case (N)
adder_1bit adder1(c0, sum, a0, a1, ci); //1-bit implementation
adder_2bit adder2(c0, sum, a0, a1, ci); //2-bit implementation
default: adder_cla #(N) adder3(c0, sum, a0, a1, ci); // Default is N-bit
endcase
endgenerate //end of the generate block
endmodule
Generate Case
MATRUSRI
ENGINEERING COLLEGE
A generate case is just like a case statement

1. Generate statements allow Verilog code to be generated dynamically at
elaboration time before the simulation begins.
2. Generated instances have unique identifier names.
3. Genvars do not exist during simulation of the design.
4. The value of a genvar can be defined only by a generate loop.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

CONTENTS:
Functions
Tasks
Difference between tasks and functions
Similarities between tasks and functions
OUTCOMES:
Students will be able to
•Identify the conditions required for tasks and function to be defined.
•Understand task/ function declaration and invocation.
MODULE-VII: Tasks and Functions
MATRUSRI
ENGINEERING COLLEGE

Keyword: function, endfunction
•Can be used if the procedure
odoes not have any timing control constructs
oreturns exactly a single value
ohas at least one input argument
Functions
MATRUSRI
ENGINEERING COLLEGE
Declaration syntax:
function <range_or_type> <func_name>;
<input declaration(s)>
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end // if begin used
endfunction
Invocation syntax:
<func_name> (<argument(s)>);

•Much like function in Pascal
•An internal implicit reg is declared inside the function with same name
•The return value is specified by setting that implicit reg
•<range_or_type> defines width and type of the implicit reg
o<type> can be integer or real
odefault bit width is 1
Functions
MATRUSRI
ENGINEERING COLLEGE
module parity;
reg [31:0] addr; reg parity;
initial begin
…
end
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b",
calc_parity(addr));
end
function calc_parity;
input [31:0] address;
begin
calc_parity = ^address;
end
endfunction
endmodule

module shifter;
`define LEFT_SHIFT 1'b0
`define RIGHT_SHIFT 1'b1
reg [31:0] addr, left_addr, right_addr;
reg control;
initial
begin
…
end
always @(addr)
begin
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr,`RIGHT_SHIFT);
end
Controllable Shifter
MATRUSRI
ENGINEERING COLLEGE
function [31:0] shift;
input [31:0] address;
input control;
begin
shift = (control==`LEFT_SHIFT)
?(address<<1) : (address>>1);
end
endfunction
endmodule

module parity;
...
reg [31:0] addr;
reg parity;
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b", calc_parity(addr) );
end
...
function functioncalc_parity; input [31:0] address;
begin
calc_parity = ^address;
end
endfunction
...
endmodule
Parity Calculation
MATRUSRI
ENGINEERING COLLEGE

Keywords: task, endtask
•Must be used if the procedure has
oany timing control constructs
ozero or more than one output arguments
ono input arguments
Task
MATRUSRI
ENGINEERING COLLEGE
Declaration syntax
task <task_name>;
<I/O declarations>
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask
Task invocation syntax
<task_name>;
<task_name> (<arguments>);

•input and inout arguments are passed into the task
•output and inout arguments are passed back to the invoking statement when
task is completed
I/O declaration in modules vs. tasks
•Both used keywords: input, output, inout
•In modules, represent ports: connect to external signals
•In tasks, represent arguments: pass values to and from the task
Task
MATRUSRI
ENGINEERING COLLEGE
module operation;
parameter delay = 10;
reg [15:0] A, B;
reg [15:0] AB_AND, AB_OR, AB_XOR;
initial
$monitor( …);
initial
begin
…
end
always @(A or B)
begin
bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B);
end
task bitwise_oper;
output [15:0] ab_and, ab_or,
ab_xor;
input [15:0] a, b;
begin
#delay ab_and = a & b;
ab_or = a | b;
ab_xor = a ^ b;
end
endtask
endmodule

module sequence;
reg clock;
initial
begin
…
end
initial
init_sequence;
always
asymmetric_sequence;
Use of module local variables
MATRUSRI
ENGINEERING COLLEGE
task init_sequence;
clock = 1'b0;
endtask
task asymmetric_sequence;
begin
#12 clock = 1'b0;
#5 clock = 1'b1;
#3 clock = 1'b0;
#10 clock = 1'b1;
end
endtask
endmodule

Differences between Tasks and Functions
MATRUSRI
ENGINEERING COLLEGE
Functions Tasks
Can enable another function but not
another task
Can enable other tasks and functions
Always execute in 0 simulation time May execute in non-zero simulation
simulation time
Must not contain any delay, control
statements.
May contain delay, event, or timing
event, or timing control statements.
Must have at least one input
argument. They can have more than
one
May have zero or more arguments of
type input, output, or inout.
Always return a single value. They
cannot have output or inout
arguments.
Do not return with a value, but can
pass multiple values through output
and inout arguments.

Both
•are defined in a module
•are local to the module
•can have local variables (registers, but not nets) and events
•contain only behavioral statements
•do not contain initial or always statements
•are called from initial or always statements or other tasks or functions
Similarities between Tasks and Functions
MATRUSRI
ENGINEERING COLLEGE
•Tasks can be used for common Verilog code
•Function are used when the common code
ois purely combinational
oexecutes in 0 simulation time
oprovides exactly one output
•Functions are typically used for conversions and commonly used calculations

1. Tasks and functions are used to reduce code repetition.
2. Tasks can have any number of inputs and outputs.
3. Functions can have any number of inputs but only one output.
4. Functions can call other functions, but cannot call tasks.
5. Task can include time delays.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

CONTENTS:
ALU
Encoder
Decoder
Multiplexer
Demultiplexer
Parity generator/checker
OUTCOMES:
Students should be able to Use behavioral modeling statements in practical
examples.
MODULE-VIII: Combinational Logic Modules
MATRUSRI
ENGINEERING COLLEGE

ALU
MATRUSRI
ENGINEERING COLLEGE
Operation
Inputs Outputs
s[2]s[1]s[0] F
Clear 000 0000
B-A 001 B-A
A-B 010 A-B
ADD 011 A+B
XOR 100 A XOR B
OR 101 A OR B
AND 110 A AND B
Preset 111 1111

ALU
MATRUSRI
ENGINEERING COLLEGE
module ALU4bit (S, A, B, F);
input [2:0] S;
input [3:0] A, B;
output reg [3:0] F;
always @(S, A, B)
case (S)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
default:
$display(“Invalid ALU control signal.”);
endcase
endmodule
module ALU4btest_v;
reg [2:0] S;
reg [3:0] A;
reg [3:0] B;
wire [3:0] F;
ALU4bit uut(.s(s),.A(A),.B(B),.F(F));
initial begin
A= 4'b1100;
B= 4'b0101;
S=0;
#10 S=1; #10 S=2;
#10 S=3; #10 S=4;
#10 S=5; #10 S=6;
#10 S=7;
end
endmodule

Encoder
MATRUSRI
ENGINEERING COLLEGE

Encoder
MATRUSRI
ENGINEERING COLLEGE
Dataflow
module encoder83behv(a, y);
input [7:0] a; output [2:0] y;
assign y[0] = a[1] | a[3] | a[5] | a[7];
assign y[1] = a[2] | a[3] | a[6] | a[7];
assign y[2] = a[4] | a[5] | a[6] | a[7];
endmodule
Behavioural
module encoder83behv(a, y);
input [7:0] a; output reg[2:0] y;
always @(a)
case (a)
8'b00000001: y = 3'b000;
8'b00000010: y = 3'b001;
8'b00000100: y = 3'b010;
8'b00001000: y = 3'b011;
8'b00010000: y = 3'b100;
8'b00100000: y = 3'b101;
8'b01000000: y = 3'b110;
8'b10000000: y = 3'b111;
default: y = 3'b000;
endcase
endmodule
Testbench
module encoder83btb;
reg [7:0] a;
wire [2:0] y;
encoder83behv uut (.a(a), .y(y));
initial
begin
// Initialize Inputs
a =8'b00000001;
#10 a=8'b00000010;
#10 a=8'b00000100;
#10 a=8'b00001000;
#10 a=8'b00010000;
#10 a=8'b00100000;
#10 a=8'b01000000;
#10 a=8'b10000000;
end
endmodule

Decoder
MATRUSRI
ENGINEERING COLLEGE

Decoder
MATRUSRI
ENGINEERING COLLEGE
Dataflow
module decoder(a, en, y);
input [2:0] a;
input en;
output [7:0] y;
assign y [7] = a[2] & a[1]& a[0] &en;
assign y [6] = a[2] & a[1]& ~a[0] &en;
assign y [5] = a[2] & ~a[1]& a[0] &en;
assign y [4] = a[2] & ~a[1]& ~a[0] &en;
assign y [3] = ~a[2] & a[1]& a[0] &en;
assign y [2] = ~a[2] & a[1]& ~a[0] &en;
assign y [1] = ~a[2] & ~a[1]& a[0] &en;
assign y [0] = ~a[2] & ~a[1]& ~a[0] &en;
endmodule
Behavioural
module decoder (a, en, y);
input [2:0] a;
input en;
output reg [7:0] y;
always @(a)
begin
if(en)
case (a)
3'b000 : y= 8'b00000001;
3'b001 : y = 8'b00000010;
3'b010 : y = 8'b00000100;
3'b011 : y = 8'b00001000;
3'b100 : y = 8'b00010000;
3'b101 : y = 8'b00100000;
3'b110 : y= 8'b01000000;
3'b111 : y = 8'b10000000;
endcase
else
y= 8’b00000000;
end
endmodule

Decoder
MATRUSRI
ENGINEERING COLLEGE
Testbench
module Decodertb;
// Inputs
reg [2:0] a;
reg en;
/ Outputs
wire [7:0] y;
// Instantiate the Unit Under Test (UUT)
decoderb38 uut (
.a(a),
.y(y)
);
initial
begin
en=1;
a = 3'b000;
// Wait 100 ns for global reset to finish
#100;a= 3'b100;
// Wait 100 ns for global reset to finish
#100;a= 3'b111;
end
endmodule

Multiplexer
MATRUSRI
ENGINEERING COLLEGE

Behavioural
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output reg out;
input i0, i1, i2, i3;
input s1, s0;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
endmodule
Dataflow
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out= s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
endmodule
Multiplexer
MATRUSRI
ENGINEERING COLLEGE
Testbench
module muxtb;
reg [1:0] s;
reg [3:0] i;
wire out;
mux4_to_1 uut
(out, i0, i1, i2, i3, s1, s0);
initial
begin
{i0,i1,i2,i3} = 4'b1010;
{s1,s0} = 2'b00;
#10 {s1,s0} = 2'b01;
#10 {s1,s0} = 2'b10;
#10 {s1,s0} = 2’b11;
end
endmodule

Demultiplexer
MATRUSRI
ENGINEERING COLLEGE

Demultiplexer
MATRUSRI
ENGINEERING COLLEGE
Behavioural
module demultiplexer1_to_4(out0, out1, out2, out3, in, s1, s0);
output reg out0, out1, out2, out3;
input in, s1, s0;
always @(sl or s0 or in)
case ({s1, s0)) //Switch based on control signals
2 'b00 : begin
out0 = in; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
2’b01 : begin
out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end
2’b10 : begin
out0 = 1'bz; out1 = 1'bz; out2 = in; out3 = 1'bz; end
2’b11 : begin
out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = in; end
2'bx0, 2’bx1, 2'bxz, 2'bxx, 2’b0x, 2’b1x, 2'bzx : begin
out0 = 1'bx; out1 = 1'bx; out2 = 1'bx; out3 = 1'bx; end
2'bz0, 2’bz1, 2'bzz, 2’b0z, 2’b1z : begin
out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
default: $display("Unspecified control signals");
endcase
endmodule

Demultiplexer
MATRUSRI
ENGINEERING COLLEGE
Dataflow
module demultiplexer1_to_4(out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
input in, s1, s0;
assign out3= s[1]& s[0] &in;
assign out2= s[1]& ~s[0] &in;
assign out1= ~s[1]& s[0] &in;
assign out0= ~s[1]& ~s[0] &in;
endmodule
Testbench
module demuxtest;
reg in, s1, s0;
wire out0, out1, out2, out3;
demultiplexer1_to_4 uut(out0, out1, out2, out3, in, s1, s0);
initial begin
#10 in=1; s1=0; s0=0;
#10 s1=0; s0=1;
#10 s1=1; s0=0;
#10 s1=1; s0=1;
end
endmodule

Parity Generator/Checker
MATRUSRI
ENGINEERING COLLEGE
Parity Generator: Parity Checker:

Parity Generator
MATRUSRI
ENGINEERING COLLEGE
module pgenerator(input [7:0]a, output reg p);
integer i, count;
always@(a)
begin
count = 0;
for(i=0;i<=7;i=i+1)
begin
if (a[i] == 1)
count = count + 1;
end
if (count % 2 == 0)
begin
p = 0;
$display(“For Even Parity generator %b,{a,p});
end
else
begin
p = 1;
$display(“For Odd Parity generator %b,{a,p});
end
end
endmodule
Testbench:
module pg_tb;
reg [7:0] a;
wire p;
pgenerator uut(a,p);
initial
begin
a=8’b01001111;
#100 a= 8’b10111101;
end
endmodule

Parity Checker
MATRUSRI
ENGINEERING COLLEGE
module pchecker(input [7:0]a);
wire [8:0]g;
reg temp;
pgenerator g1(a,p);
assign g = {a,p};
always@(*)
begin
temp <= ^g;
if(temp)
$display(“ODD Parity);
else
$display(“EVEN Parity);
end
endmodule
Testbench:
module pc_tb;
reg [7:0] a;
pchecker uut(a);
initial
Begin
a=8’b01001111;
#100 a= 8’b10111101;
end
endmodule

1. ALU is the fundamental building block of the processor, which is
responsible for carrying out the arithmetic and logic functions.
2. A parity bit is an extra bit included with the binary message to make the
number of ones either even or odd.
3. A Decoder decodes an encrypted input signal to multiple output signals
from one format to another format.
4. Priority encoders can be used to reduce the number of wires needed in a
particular circuits or application that have multiple inputs.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

CONTENTS:
Bus Structure
OUTCOMES:
Student will able to design the structure of bus.
MODULE-IX: Bus Structure
MATRUSRI
ENGINEERING COLLEGE

Bus Structure
MATRUSRI
ENGINEERING COLLEGE
A digital system with k registers.

Bus Structure
MATRUSRI
ENGINEERING COLLEGE
module swap (Data, Resetn, w, Clock, Extern, RinExt, BusWires);
input [7:0] Data;
input Resetn, w, Clock, Extern;
input [1:3] RinExt;
output [7:0] BusWires;
tri [7:0] BusWires;
wire [1:3] Rin, Rout, Q;
wire [7:0] R1, R2, R3;
shiftr control (Resetn, w, Clock, Q);
defparam control.m = 3;
assign Rin[1] = RinExt[1] | Q[3];
assign Rout[1] = Q[2];
regn reg 1 (BusWires, Rin[1], Clock, R1);
trin tri ext (Data, Extern, BusWires);
trin tri 1 (R1, Rout[1], BusWires);
endmodule

Bus Structure
MATRUSRI
ENGINEERING COLLEGE
Code for an n-bit register:
module regn (R, Rin, Clock, Q);
parameter n = 8;
input [n-1:0] R;
input Rin, Clock;
output reg [n-1:0] Q;
always @(posedge Clock)
if (Rin)
Q <= R;
endmodule
Code for an n-bit tri-state:
module trin (Y, E, F);
parameter n = 8;
input [n-1:0] Y;
input E;
output [n-1:0] F;
assign F=E?Y: ’bz;
endmodule

Bus Structure
MATRUSRI
ENGINEERING COLLEGE
A shift-register control circuit.
module shiftr (Resetn, w, Clock, Q);
parameter m = 4;
input Resetn, w, Clock;
output [1:m] Q; reg [1:m] Q;
integer k;
always @(negedge Resetn or posedge Clock)
if (!Resetn)
Q <= 0;
else
begin
for (k = m; k > 1 ; k = k -1)
Q[k] <= Q[k -1];
Q[1] <= w;
end
endmodule

Bus Structure
MATRUSRI
ENGINEERING COLLEGE
A modified control circuit:
A modified version of
the circuit:

Bus Structure (Using multiplexers)
MATRUSRI
ENGINEERING COLLEGE
module swapmux (
Data, Resetn, w,
Clock, RinExt, BusWires);
input [7:0] Data;
input Resetn, w, Clock;
input [1:3] RinExt;
output reg [7:0] BusWires;
wire [1:3] Rin, Q;
wire [7:0] R1, R2, R3;
reg [1:0] S;
shiftr control (Resetn, w, Clock, Q);
defparam control.m = 3;

Bus Structure
MATRUSRI
ENGINEERING COLLEGE
always @(Q or Data or R1 or R2 or R3 or S)
begin
// Encoder
if (Q == 3’b000)
S = 2’b00;
else if (Q == 3’b100)
S = 2’b10;
else if (Q == 3’b010)
S = 2’b01;
else
S=2’b11;
// Multiplexers
if (S == 2’b00)
BusWires = Data;
else if (S == 2’b01)
BusWires = R1;
else if (S == 2’b10)
BusWires = R2;
else
BusWires = R3;
end
endmodule

1. Common set of wires is usually called a bus.
2. Different flip-flops will be clocked at slightly different times, leading to a
problem known as clock skew.
3. tri-state buffers are used to control access to the bus.
4. PLDs, do not contain a sufficient number of tri-state buffers to realize even
moderately large buses.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

CONTENTS:
Static Timing Analysis
Logic synthesis
Verilog Costructs
Synthesis Design flow
OUTCOMES:
Student will able to
•Explain the benefits of static timing analysis.
•Understand how the logic synthesis tool interprets these constructs.
•Describe the components in the logic synthesis-based design flow.
MODULE-X: Static Timing Analysis
MATRUSRI
ENGINEERING COLLEGE

MATRUSRI
ENGINEERING COLLEGE
0% 100%
Timing Simulation
(adding vectors)
Static timing analysis
(eliminating false paths)
True timing paths False timing paths
STA approach typically takes a fraction of the time it takes to run logic
simulation on a large design and guarantees 100% coverage of all true timing
paths in the design without having to generate test vectors
Effective methodology for verifying the timing characteristics of a design
without the use of test vectors
Conventional verification techniques are inadequate for complex designs
•Simulation time using conventional simulators
oThousands of test vectors are required to test all timing paths using
logic simulation
• Increasing design complexity & smaller process technologies
oIncreases the number of iterations for STA

MATRUSRI
ENGINEERING COLLEGE
• Requires extensive vector creation
• Valid for FPGAs and smaller ASICs
• Falls apart on multi-million gate ASICs

Static Timing Analysis is a method for determining if a circuit meets timing
constraints without having to simulate
• Much faster than timing-driven, gate-level simulation
• Proper circuit functionality is not checked
• Vector generation NOT required
MATRUSRI
ENGINEERING COLLEGE
Advantages
• Fast, exhaustive
• Better analysis checks against timing requirements
Disadvantage
• Less accurate
• Must define timing requirements/exceptions
• Difficulty handling asynchronous designs, false paths
Three Steps in Static Timing Analysis:
• Circuit is broken down into sets of timing paths
• Delay of each path is calculated
• Path delays are checked to see if timing constraints have been met

Logic synthesis
MATRUSRI
ENGINEERING COLLEGE
Designer's Mind Basic Computer-Aided

Verilog Constructs for Logic Synthesis
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ENGINEERING COLLEGE
Construct Type Keyword or Description Notes
Ports input, inout, output
Parameter parameter
Module Definition module
signals and Variables wire, reg, tri Vectors are allowed
Instantiation module instances,
primitive gate instances
E.g., mymux m1(out, i0, i1, s);
E.g., nand (out, a, b);
functions and Tasks function, task Timing constructs ignored
Procedural always, if, then, else, case,
casex, casez
initial is not supported
Procedural Blocks begin, end, named blocks,
disable
Disabling of named blocks
allowed
data flow assign Delay information is ignored
Loops for, while, forever, while and forever loops must
contain @(posedge clk) or
@(negedge clk)

Logic Synthesis Flow:
Synthesis Design Flow
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ENGINEERING COLLEGE

1. Logic synthesis is the process of converting a high-level description of the
design into an optimized gate-level representation, given a standard cell
library and certain design constraints.
2. A standard cell library is also known as the technology library.
3. Logic synthesis improves productivity by reducing design cycle time.
4. Operators such as === and !== that are related to x and z are not allowed
for logic synthesis.
Questions & Answers
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ENGINEERING COLLEGE

CONTENTS:
Procedural Continuous Assignment
OUTCOMES:
Student will able to
•Describe procedural continuous assignment statements.
•Explain their significance in modeling and debugging. .
MODULE-XI: Additional Topic
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ENGINEERING COLLEGE

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ENGINEERING COLLEGE
Overrides, for a certain time, the effect of regular assignments to a variable.
Two types
•assign/deassign: Works only on register data types
•force/release: Works on both register and net data types
Note: Not synthesizable. Use only for modeling and simulation
assign/deassign
Keywords
assign: overrides regular procedural assignments
oLHS: reg or concatenation of regs.
oNo nets.
oNo arrays.
oNo bit-select or part-select
deassign: re-enables regular procedural assignments
After deassign: Last value remains on the register until a new
procedural assignment changes it.

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ENGINEERING COLLEGE
module edge_dff(q, qbar, d, clk, reset);
output reg q,qbar;
input d, clk, reset;
always @(negedge clk)
begin
q = d;
qbar = ~d;
end
always @(reset)
if(reset)
begin
assign q = 1'b0; assign qbar = 1'b1;
end
else
begin
deassign q; deassign qbar;
end
endmodule

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ENGINEERING COLLEGE
force/release
Keywords:
•force: overrides all procedural/continuous/ procedural continuous
assignments
•release: re-enables other assignments
•Hence, assignments in priority order:
1. force
2. assign (procedural continuous)
3. Procedural/continuous assignments
module stimulus;
...
edge_dff dff(Q, Qbar, D, CLK, RESET);
initial begin
#50 force dff.q = 1'b1;
#50 release dff.q;
end
...
endmodule
module top;
... ...
assign out = a & b & c;
...
initial begin
#50 force out = a | b & c;
#50 release out;
end
... endmodule

1. Procedural continuous assignments override existing assignments to a
register or net.
2. Procedural continuous assignments are normally used for controlled
periods of time.
3. Force and release statements are typically used in the interactive
debugging process.
4. Force and release statements not be used inside design blocks.
Questions & Answers
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ENGINEERING COLLEGE

Question Bank
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ENGINEERING COLLEGE
Short Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 What are the differences between regular switches and
resistive switches.
L1 CO2
2 Write the Verilog code for CMOS NOR in switch level model. L1 CO2
3 Write differences between tasks and functions. L1 CO2
4 Write a verilog code to get a square wave with 60% duty cycle. L1 CO2
5 What is the difference between always block and initial block. L1 CO2
6 What are time delays with switch primitives. L2 CO2
7 Describe multiway branching, using case, case x and case z
statements.
L4 CO2
8 Write a verilog code for 2x1 mux in switch level modeling. L1 CO2
9 What are the continuous and procedural assignments? How
these two are differed?
L1 CO2
10 What are design constraints for logic synthesis? L4 CO2
11 Write short notes on sequential and parallel blocks. L1 CO2

Question Bank
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ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 How to convert parallel block into sequential block? Explain
with example.
L2 CO2
2 Write a verilog program for 16:1 mux using functions. L1 CO2
3 Write a verilog code for 4-bit ripple carry adder using generate
statement.
L1 CO2
4 Write a verilog program for 8x3 priority encoder. Write its test
bench.
L1 CO2
5 Write a verilog program for 16-bit ALU with 8-instructions
using case statement.
L1 CO2
6 Explain the various Delay-based timing controls with example. L2 CO2
7 Write the Verilog code for 3-bit parity generator & checker . L1 CO2
8 Explain Logic synthesis flow. L5 CO2
9 Explain force and release statements with example. L2 CO2
10 What are conditional statements in verilog? Give one example L1 CO2
11 Discuss about different types of generate blocks with syntax. L5 CO2
12 Briefly explain Bus structure using a neat diagram and
implement it in Verilog.
L5 CO2

Assignment Questions
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ENGINEERING COLLEGE
1. Write a verilog program for Parity generation for 4-bit number using
functions and task.
2. Explain about types of timing controls in verilog with syntax and one
example for each.
3. What is the difference between blocking assignments and non blocking
assignments ? Give one example.
4. Write a verilog code for 4x1 mux in switch level modeling and verity its
functionality using testbench.
5. Explain synthesis design flow.

Digital System Design-Switchlevel and Behavioural Modeling

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