Ch4 Boolean Algebra And Logic Simplication1

Ch. 4 Boolean Algebra and Logic Simplification Boolean Operations and Expressions Laws and Rules of Boolean Algebra Boolean Analysis of Logic Circuits Simplification Using Boolean Algebra Standard Forms of Boolean Expressions Truth Table and Karnaugh Map Programmable Logic: PALs and GALs Boolean Expressions with VHDL

Introduction Boolean Algebra George Boole(English mathematician), 1854 “ An Investigation of the Laws of Thought, on Which Are Founded the Mathematical Theories of Logic and Probabilities” Boolean Algebra {(1,0), Var, (NOT, AND, OR), Thms} Mathematical tool to expression and analyze digital (logic) circuits Claude Shannon, the first to apply Boole’s work, 1938 “ A Symbolic Analysis of Relay and Switching Circuits” at MIT This chapter covers Boolean algebra, Boolean expression and its evaluation and simplification, and VHDL program

Boolean functions : NOT, AND, OR, exclusive OR(XOR) : odd function exclusive NOR(XNOR) : even function(equivalence) Basic Functions

AND Z=X  Y or Z=XY Z=1 if and only if X=1 and Y=1 , otherwise Z=0 OR Z=X + Y Z=1 if X=1 or if Y=1, or both X=1and Y=1. Z=0 if and only if X=0 and Y=0 NOT Z=X  or Z=1 if X=0, Z=0 if X=1 Basic Functions ( 계속 )

Boolean Operations and Expressions Boolean Addition Logical OR operation Ex 4-1) Determine the values of A, B, C, and D that make the sum term A+B’+C+D’ Sol) all literals must be ‘0’ for the sum term to be ‘0’ A+B’+C+D’=0+1’+0+1’=0  A=0, B=1, C=0, and D=1 Boolean Multiplication Logical AND operation Ex 4-2) Determine the values of A, B, C, and D for AB’CD’=1 Sol) all literals must be ‘1’ for the product term to be ‘1’ AB’CD’=10’10’=1  A=1, B=0, C=1, and D=0

Basic Identities of Boolean Algebra The relationship between a single variable X, its complement X  , and the binary constants 0 and 1

Laws of Boolean Algebra Commutative Law the order of literals does not matter A + B = B + A A B = B A

Associative Law the grouping of literals does not matter A + (B + C) = (A + B) + C (=A+B+C) A(BC) = (AB)C (=ABC) Laws of Boolean Algebra ( 계속 )

Distributive Law : A(B + C) = AB + AC Laws of Boolean Algebra ( 계속 ) A B C X Y X=Y

(A+B)(C+D) = AC + AD + BC + BD Laws of Boolean Algebra ( 계속 ) A B C D X Y X=Y

A+0=A In math if you add 0 you have changed nothing in Boolean Algebra ORing with 0 changes nothing A X X=A+0=A Rules of Boolean Algebra

A+1=1 ORing with 1 must give a 1 since if any input is 1 an OR gate will give a 1 Rules of Boolean Algebra ( 계속 ) A X X=A+1=1

A•0=0 In math if 0 is multiplied with anything you get 0. If you AND anything with 0 you get 0 Rules of Boolean Algebra ( 계속 ) A X X=A0 = 0

A•1 =A ANDing anything with 1 will yield the anything Rules of Boolean Algebra ( 계속 ) A X X=A1=A A

A+A = A ORing with itself will give the same result Rules of Boolean Algebra ( 계속 ) A A X A=A+A =A

A+A’=1 Either A or A’ must be 1 so A + A’ =1 Rules of Boolean Algebra ( 계속 ) A A’ X X=+A’=1

A•A = A ANDing with itself will give the same result Rules of Boolean Algebra ( 계속 ) A A X A=AA=A

A•A’ =0 In digital Logic 1’ =0 and 0’ =1, so AA’=0 since one of the inputs must be 0. Rules of Boolean Algebra ( 계속 ) A A’ X X=AA’=0

A = (A’)’ If you not something twice you are back to the beginning Rules of Boolean Algebra ( 계속 ) A X X=(A’)’=A

Rules of Boolean Algebra ( 계속 ) A B X A + AB = A

A + A’B = A + B If A is 1 the output is 1 If A is 0 the output is B Rules of Boolean Algebra ( 계속 ) A B X Y X=Y

Rules of Boolean Algebra ( 계속 ) A B C X Y (A + B)(A + C) = A + BC

DeMorgan’s Theorem F  (A,A  ,  , + , 1,0) = F(A  , A, + ,  ,0,1) (A • B)’ = A’ + B’ and (A + B)’ = A’ • B’ DeMorgan’s theorem will help to simplify digital circuits using NORs and NANDs his theorem states DeMorgan’s Theorems

Look at (A +B +C + D)’ = A’ • B’ • C’ • D’

Ex 4-3) Apply DeMorgan’s theorems to (XYZ)’ and (X+Y+Z)’ Sol) (XYZ)’=X’+Y’+Z’ and (X+Y+Z)’=X’Y’Z’ Ex 4-5) Apply DeMorgan’s theorems to (a) ((A+B+C)D)’ (b) (ABC+DEF)’ (c) (AB’+C’D+EF)’ Sol) (a) ((A+B+C)D)’= (A+B+C)’+D’=A’B’C’+D’ (b) (ABC+DEF)’=(ABC)’(DEF)’=(A’+B’+C’)(D’+E’+F’) (c) (AB’+C’D+EF)’=(AB’)’(C’D)’(EF)’=(A’+B)(C+D’)(E’+F’)

Boolean Analysis of Logic Circuits Boolean Expression for a Logic Circuit Figure 4-16 A logic circuit showing the development of the Boolean expression for the output.

Constructing a Truth Table for a Logic Circuit Convert the expression into the min-terms containing all the input literals Get the numbers from the min-terms Putting ‘1’s in the rows corresponding to the min-terms and ‘0’s in the remains Ex) A(B+CD)= AB(C+C’) (D+D’) +A(B+B’)CD = ABC(D+D’) +ABC’(D+D’) +ABCD+AB’CD = ABCD +ABCD’+ABC’D+ABC’D’ + ABCD +AB’CD = ABCD +ABCD’+ABC’D+ABC’D’ +AB’CD =m11+m12+m13+m14+m15=  (11,12,13,14,15)

Truth Table from Logic Circuit A(B+CD)=m11+m12+m13+m14+m15 =  (11,12,13,14,15) Output Input 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 A(B+CD) D C B A

Ex 4-8) Using Boolean algebra, simplify this expression AB+A(B+C)+B(B+C) Sol) AB+AB+AC+BB+BC =B(1+A+A+C)+AC= B+AC Simplification Using Boolean Algebra

Ex 4-9) Simplify the following Boolean expression (AB’(C+BD)+A’B’)C Sol) (AB’C+ A B’B D +A’B’)C=A B’CC +A’ B’C =(A+A’)B’C=B’C Ex 4-10) Simplify the following Boolean expression A’ BC +A B’C’ +A’ B’C’ +AB’C+A BC Sol) (A+A’) BC +(A+A’) B’C’ +AB’C=BC+ B’ C’+A B’ C =BC+B’(C’+AC)=BC+B’(C’+A)=BC+B’C’+AB’ Ex 4-11) Simplify the following Boolean expression (AB +AC)’+A’B’C Sol) (AB)’(AC)’+A’B’C=(A’+ B’)(A’+C’)+ A’ B’C =A’+A’B’ +A’C’+B’C+A’B’C =A’(1+B’+C’+B’C)+B’C=A’+B’C’

Standard Forms of Boolean Expressions The Sum-of-Products(SOP) Form Ex) AB+ABC, ABC+CDE+B’CD’ The Product-of-Sums(POS) Form Ex) (A+B)(A+B+C), (A+B+C)(C+D+E)(B’+C+D’) Principle of Duality : SOP  POS Domain of a Boolean Expression The set of variables contained in the expression Ex) A’B+AB’C : the domain is {A, B, C}

Implementation of a SOP Expression AND-OR logic Conversion of General Expression to SOP Form A(B+CD)=AB +ACD Ex 4-12) Convert each of the following expressions to SOP form: (a) AB+B(CD+EF) (b) (A+B)(B+C+D) Sol) (a) AB+B(CD+EF)=AB+BCD+BEF (b) (A+B)(B+C+D)=AB+AC+AD+ BB+BC+BD =B(1+A+C+D)+ AC+AD=B+AC+AD

Standard SOP Form (Canonical SOP Form) For all the missing variables, apply (x+x’)=1 to the AND terms of the expression List all the min-terms in forms of the complete set of variables in ascending order Ex 4-13) Convert the following expression into standard SOP form: AB’C+A’B’+ABC’D Sol) domain={A,B,C,D}, AB’C(D’+D)+A’B’(C’+C)(D’+D)+ABC’D =AB’CD’+AB’CD+A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD+ABC’D =1010+1011+0000+0001+0010+0011+1101 =0+1+2+3+10+11+13 =  (0,1,2,3,10,11,13)

Product-of-Sums Form Implementation of a POS Expression OR-AND logic

Standard POS Form (Canonical POS Form) For all the missing variables, apply (x’x)=0 to the OR terms of the expression List all the max-terms in forms of the complete set of variables in ascending order Ex 4-15) Convert the following expression into standard POS form: (A+B’+C)(B’+C+D’)(A+B’+C’+D) Sol) domain={A,B,C,D}, (A+B’+C)(B’+C+D’)(A+B’+C’+D) =(A+B’+C+D’D)(A’A+B’+C+D’)(A+B’+C’+D) = (A+B’+C+D’) (A+B’+C+D) (A’+B’+C+D’) (A+B’+C+D’)(A+B’+C’+D)=(0100) )(0101)(0110)(1101)=  (4,5,6,13)

Converting Standard SOP to Standard POS Step 1. Evaluate each product term in the SOP expression. Determine the binary numbers that represent the product terms Step 2. Determine all of the binary numbers not included in the evaluation in Step 1 Step 3. Write in equivalent sum term for each binary number Step 2 and expression in POS form Ex 4-17) Convert the following SOP to POS Sol) SOP= A’B’C’+A’BC’+A’BC+AB’C+ABC=0+2+3+5+7 =  (0,2,3,5,7) POS=(1)(4)(6) =  (1, 4, 6) (=(A+B+C’)(A’+B+C)(A’+B’+C))

Boolean Expressions and Truth Tables Converting SOP Expressions to Truth Table Format Ex 4-18) A’B’C+AB’C’+ABC =  (1,4,7) ABC 1 1 1 1 0 1 1 0 0 1 0 1 AB’C’ 1 1 0 0 0 0 1 1 0 0 1 0 A’B’C 1 0 0 1 0 0 0 0 Product Term Output X Inputs A B C

Converting POS Expressions to Truth Table Format Ex 4-19) (A+B+C)(A+B’+C)(A+B’+C’)(A’+B+C’)(A’+B’+C) = (000)(010)(011)(101)(110) =  (0,2,3,5,6) 1 1 1 1 A’+B’+C 0 1 1 0 A’+B+C’ 0 1 0 1 1 1 0 0 A+B’+C’ 0 0 1 1 A+B’+C 0 0 1 0 1 0 0 1 A+B+C 0 0 0 0 Sum Term Output X Inputs A B C

Ex 4-20) Determine standard SOP and POS from the truth table Sol) (a) Standard SOP F=A’BC+AB’C’+ABC’+ABC (b) Standard POS F=(A+B+C)(A+B+C’)(A+B’+C) (A’+B+C’) 1 1 1 1 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Output X Inputs A B C

Boolean Expression Truth Table Logic Diagram

Karnaugh Map Simplification methods Boolean algebra(algebraic method) Karnaugh map(map method)) Quine-McCluskey(tabular method) XY+XY  =X(Y+Y  )=X

Three- and Four-input Kanaugh maps Gray code

F(X,Y,Z)=  m(0,1,2,6) =(XY  +YZ)  =X’Y’ + YZ’

Example) F(X,Y,Z)=  m(2,3,4,5) =X  Y+XY  0 1 3 2 4 5 7 6

Example) F(X,Y,Z)=  m(0,2,4,6) = X  Z  +XZ  =Z  (X  +X)=Z 

Four-Variable Map 16 minterms : m 0 ~ m 15 Rectangle group 2-squares(minterms) : 3-literals product term 4-squares : 2-literals product term 8-squares : 1-literals product term 16-squares : logic 1

F(W, X,Y,Z)=  m(0,2,7,8,9,10,11) = WX’ + X’Z’ + W’XYZ

Karnaugh Map SOP Minimization Mapping a Standard SOP Expression

Mapping a Nonstandard SOP Expression Numerical Expression of a Nonstandard Product Term Ex 4-23) A’+AB’+ABC’ A’ AB’ ABC’ 0 00 10 0 110 0 01 10 1 0 10 0 11

Ex 4-24) B’C’+AB’+ABC’+AB’CD’+A’B’C’D+AB’CD B’C’ AB’ ABC’ AB’CD’ A’B’C’D AB’CD 0000 1000 1100 1010 0001 1011 0001 1001 1101 1000 1010 1001 1011

Karnaugh Map Simplification of SOP Expressions Group 2 n adjacent cells including the largest possible number of 1s in a rectangle or square shape, 1<=n Get the groups containing all 1s on the map for the expression Determine the minimum SOP expression form map

Ex 4-27) (a) AB+BC+A’B’C’ (b) B’+AC+A’C’ (c) A’C’+A’B+AB’D (d) D’+BC’+AB’C

Ex 4-28) Minimize the following expression AB’C+A’BC+A’B’C+A’B’C’+AB’C’ Sol) B’+A’C

Ex 4-29) Minimize the following expression B’C’D’ +A’BC’D’+ABC’D’+A’B’CD+AB’CD+A’B’CD’+A’BCD’ +ABCD’+AB’CD’ Sol) D’+B’C

Mapping Directly from a Truth Table

Don’t Care Conditions it really does not matter since they will never occur(its output is either ‘0’ or ‘1’) The don’t care terms can be used to advantage on the Karnaugh map

Karnaugh Map POS Minimization Use the Duality Principle F(A,A  ,  , + , 1,0)  F * (A,A  , + ,  ,0,1) SOP  POS

Ex 4-30) (A’+B’+C+D)(A’+B+C’+D’)(A+B+C’+D) (A’+B’+C’+D’)(A+B+C’+D’) Sol)

Ex 4-31) (A+B+C)(A+B+C’)(A+B’+C)(A+B’+C’)(A’+B’+C) Sol) (0+0+0)(0+0+1)(0+1+0)(0+1+1)(1+1+0)=A(B’+C) AC+AB’=A(B’+C)

Ex 4-32) (B+C+D) (A+B+C’+D)(A’+B+C+D’)(A+B’+C+D)(A’+B’+C+D) Sol) (B+C+D)=(A’A+B+C+D)=(A’+B+C+D)(A+B+C+D) (1+0+0+0)(0+0+0+0)(0+0+1+0)(1+0+0+1)(0+1+0+0)(1+1+0+0) F=(C+D)(A’+B+C)(A+B+D)

Converting Between POS and SOP Using the K-map Ex 4-33) (A’+B’+C+D)(A+B’+C+D)(A+B+C+D’)(A+B+C’+D’) (A’+B+C+D’)(A+B+C’+D) Sol)

Five/Six –Variable K-Maps Five Variable K-Map : {A,B,C,D,E} 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26 00 01 11 10 00 01 11 10 BC DE A=0 A=1

Six Variable K-Map : {A,B,C,D,E,F} 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 16 17 19 18 20 21 23 22 28 29 31 30 24 25 27 26 00 01 11 10 00 01 11 10 CD EF AB 32 33 35 34 36 37 39 38 44 45 47 46 40 41 43 42 48 49 51 50 52 53 55 54 60 61 62 63 56 57 59 58 00 10 01 11

Ex 4-34) Sol) A’D’E’+B’C’D’+BCD+ACDE

Programmable Logic: PALs and GALs Basic PAL Operation Programmable array of AND gates Fixed OR gate

Implementing a Sum-of-Product Expression

Ex 4-35) Show how a PAL is programmed for the following function : X=AB’C+A’BC’+A’B’+AC Sol)

PAL Output Combinational Logic X  0=X X  1=X’

A Specific PAL Figure 4-50 Block diagram of the PAL16L8 .

Basic GAL Operation Reprogrammable AND array Electrically Erasable CMOS(E 2 CMOS) technology

Figure 4-52 GAL implementation of a sum-of-products expression.

Ex 4-36) Show how a GAL is programmed for the function: X=A’BC’+A’BC+BC+AB’ Sol)

The GAL Block Diagram OLMCs(Output Logic Macrocells) OR array and programmable output logic Typically m and n >= 8

GAL20V8 High Performance E2CMOS PLD Generic Array Logic™

Boolean Expressions with VHDL Boolean Algebra in VHDL Programming VHDL Optimization Ex 4-37) Write a VHDL grogram for the following function: X=(AC+(BC’)’+D)’+((BC)’)’ -- Program X=(AC+(BC’)’+D)’+((BC)’)’ entity alogicft is port(A, B, C, D: in bit; X: out bit); end entity alogicft; architecture expaft of alogicft is begin X<=not((A and C) or not(B and not C) or D) or not(not B and C); end architecture expaft;

-- Program X=(AC+(BC’)’+D)’+((BC)’)’=(A’+C’)(BC’)D’+BC -- =A’BC’D’+BC’D’+BC=(A’+1)BC’D’+BC = BC’D’+BC entity alogicft is port(B, C, D: in bit; X: out bit); end entity alogicft; architecture expaft of alogicft is begin X<= (B and not C and not D) or (B and C); end architecture expaft;

Levels of Abstraction for sequential logic circuits VHDL (1) Behavioral approach : state diagram or truth table (2) Data flow approach : Boolean expression or function (3) Structure approach : logic diagram or schematic describing logic function

Digital System Application : 7-Segment LED Driver Seven-Segment LED driver

A B C D 0 1 3 2 4 5 7 6 13 15 14 8 9 11 10 g = m(2,3,4,5,6,8,9) =A+BC’+B’C+CD’ CD AB

Figure 4-59 Karnaugh map minimization of the segment- a logic expression.

Figure 4-60 The minimum logic implementation for segment a of the 7-segment display.

-- Program 7-segment driver entity sevensegdrv is port(A, B, C, D: in bit; a,b,c,d,e,f,g: out bit); end entity sevensegdrv; architecture segment of sevensegdrv is begin a<= B or D or (A and C) or (not A and not C); -- B +D+AC+A’C’ • • • • • • • • • g<= A or B and C’ or not B and C or C and not D; -- A+BC’+B’C+CD’ end architecture segment; VHDL for 7-Segment Driver

Summary Gate symbols Duality Principle F(A,A  ,  , + , 1,0)  F * (A,A  , + ,  ,0,1) DeMorgan’s Theorem F  (A,A  ,  , + , 1,0) = F(A  , A, + ,  ,0,1)

The relationship between a single variable X, its complement X  , and the binary constants 0 and 1

Sum-of-Product(SOP) form  Product-of-Sums(POS) form Standard(canonical) SOP form  Standard POS form Universal gates: NAND, NOR Don’t care conditions Karnaugh map(3, 4, 5, 6 variables) PLDs: PAL, GAL VHDL for logic expressions

Boolean Expression Truth Table Logic Diagram VHDL (HDL)

Ch4 Boolean Algebra And Logic Simplication1

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