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A transfer from I/O device to memory requires the execution of several instructions by the CPU-.pdf
- 2. I/O Interface • used to transfer information between internal storage and external I/O devices is known as I/O interface. • used to resolve the differences between CPU and peripheral • Data transfer to and from the peripherals may be done in any of the three possible ways 1. Programmed I/O 2. Interrupt- initiated I/O 3. Direct memory access( DMA)
- 3. Programmed I/O • Each data item transfer is initiated by an instruction in the program • transfer is from a CPU register and memory • constant monitoring by the CPU of the peripheral devices is necessary • I/O device does not have direct access to the memory unit. • A transfer from I/O device to memory requires the execution of several instructions by the CPU, including an input instruction to transfer the data from device to the CPU and store instruction to transfer the data from CPU to memory • In programmed I/O, the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer. • This is a time consuming process since it needlessly keeps the CPU busy
- 5. Interrupt- initiated I/O • In the previous case we saw the CPU is kept busy unnecessarily • Using an interrupt driven method for data transfer avoids this situation • Whenever it is determined that the device is ready for data transfer it initiates an interrupt request signal to the computer • Meantime, the CPU can proceed for any other program execution. • Upon detection of an external interrupt signal, the CPU stops momentarily the task that it was already performing, branches to the service program to process the I/O transfer, and then return to the task it was originally performing.
- 7. Drawbacks • Both require active intervention of the processor to transfer data between memory and the I/O module • The I/O transfer rate is limited by the speed with which the processor can test and service a device. • The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer.
- 12. Direct Memory Access (DMA) • The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU • DMA allows the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU • During DMA the CPU is idle and it has no control over the memory buses • The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit. • DMA controller is a special purpose processor which controls data transfer between memory and I/O as it generates address and control signals for memory • DMA could work even when a instruction is executing by the CPU
- 13. Data transfer flow using DMAC
- 14. Burst Transfer DMA returns the bus after complete data transfer. Steps involved are: Bus grant request time. Transfer the entire block of data at transfer rate of device because the device is usually slow than the speed at which the data can be transferred to CPU. Release the control of the bus back to CPU Tx = Time required to prepare data Ty = Time required to transfer data % of time CPU is idle/blocked = Ty/(Tx+Ty) * 100 % of time CPU is busy = Tx/(Tx+Ty) * 100
- 15. Cycle Stealing • An alternative method in which DMA controller transfers one word at a time after which it must return the control of the buses to the CPU • The CPU delays its operation only for one memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle. • Steps Involved are: 1. Buffer the byte into the buffer 2. Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request) 3. Transfer the byte (at system bus speed) 4. Release the control of the bus back to CPU. % of time CPU is idle/blocked = Ty/Tx * 100 % of time CPU is busy = Tx/Ty * 100
- 16. Interleaving DMA • The DMA controller takes over the system bus when the microprocessor is not using it. • CPU is not blocked due to DMA • Maximum time required for data transfer • Time required for data transfer : Interleaving > Cycle stealing > Burst mode • Speed of data transfer : Burst mode > cycle stealing > interleaving
- 17. Vectored Interrupts • A interrupting device inform special code to the processor to identify itself • The code/address points to the starting address of an ISR for that device • The bit size of the code may vary from 4-8 bits • The processor can immediately start processing the ISR • This scheme of handling interrupt is called as vectored Interrupts SENSE,VIT Chennai
- 18. Interrupt Priority • I / O devices are grouped into priorities order • The priority level is used. It range from high priority to low priority devices • The interrupt request from the high priority devices are served first • If two devices are sending IRQ at same time the processor resolve by priority and selects the device with highest priority • The priorities can be fixed one and programmable with privileged instruction SENSE,VIT Chennai
- 19. Cont…
- 20. Types of Priority Interrupt Handling Methods • SOFTWARE METHOD – POLLING • HARDWARE METHOD – DAISY CHAINING/SERIAL CHAINING • HARDWARE METHOD – PARALLEL CHAINING
- 21. SOFTWARE METHOD – POLLING • In this method, all interrupts are serviced by branching to the same service program. • This program then checks with each device if it is the one generating the interrupt. • The order of checking is determined by the priority that has to be set. • The device having the highest priority is checked first and then devices are checked in descending order of priority. • If the device is checked to be generating the interrupt, another service program is called which works specifically for that particular device. • The major disadvantage of this method is that it is quite slow. To overcome this, we can use hardware solution, one of which involves connecting the devices in series. This is called Daisy-chaining method.
- 23. Daisy Chaining – Priority Interrupt
- 24. Daisy Chaining – Priority Interrupt • Also called as serial chaining used to handle priority interrupt • All devices connected based on their priority • The highest priority is directly connected to the CPU’s INTACK signal • INTACK sends 1 if any request sent • If device has requested for access 1 is consumed and P0 = 0 else 1 is passed and P0 = 1 • This disables all the other low priority request • That device generates the vectored address to CPU
- 27. Centralized arbitration :Daisy Chain
- 28. Cont… • DMA sends Bus Request (BR) to the processor • If the processor is ready to grant access in responds to the BR , it sends Bus grant (BG1) signal to the first connected DMA controller Informing that, it may use the bus once it is free • The DMA controller1 receives the acknowledgement from the processor. If the DMA 1 had requested the bus it will become the bus master other wise it will forward the acknowledgement to the next DMA with BG2 signal • The mechanism of using acknowledgment if it belongs to requested one, or else forwarding the acknowledgement to the next device is called as Daisy Chain • The processor sends Bus Busy signal to prevent other device to access the bus
- 31. Parallel Chaining – Priority Interrupt
- 32. Parallel Chaining – Priority Interrupt • IST = 1 if any device has generated an interrupt • IST = 0 if none of the devices have generated an interrupt • IEN = 1 if CPU is ready to handle the interrupt • IEN = 0 if CPU is not ready to handle the interrupt • IST and IEN has to be 1 for CPU to handle interrupt • This generates 1 from the INTACK • These 3 enabled signals enable the VAD in CPU
- 33. Synchronous Bus Synchronous bus (e.g., processor-memory buses) • All devices derive timing information from a common clock. • Equal time intervals. Advantage: • It needs very little thought and can work very quickly. Disadvantages: • Every device communicating on the bus must use same clock rate • To avoid clock skew, they cannot be long if they are fast
- 34. Asynchronous Bus It is not clocked, so a handshaking protocol is required and additional control lines are needed. Advantages: • Can accommodate a wide range of devices and device speeds • Can be lengthened without worrying about clock skew or synchronization problem. Disadvantage: slow