1-AVR Introduction to Atmega32 good .pdf

AVR MICROCONTROLLER
(ATMEGA 32)
P. Pavan Kumar, Asst. Professor, MVGRCE (A)

Contents
 Introduction
 Features of ATmega32 microcontroller
 Memory organisation
 Block diagram of ATmega32

Introduction
 AVR was designed by two students of Norwegian
Institute of Technology, Alf-Egil Bogen and Vegard
Wollan, and then was bought and developed by
ATMEL in 1996.
 AVR stands for Advanced Virtual RISC or some call it
as Alf and Vegard RISC.
 Except for AVR32, which is a 32-bit microcontroller,
AVRs are all 8-bit microcontrollers, meaning that the
CPU can work only on 8-bits of data at a time.

Introduction
 One of the problems with the AVR microcontrollers is
that they are not all 100% compatible in terms of
software when going from one group to another.
 AVRs are generally classified into four broad
groups: Classic, Mega, Tiny and special purpose.
 ATmega32 is most widely used and available, which
comes in DIP.

Features of ATmega32 microcontroller
 AVR microcontrollers are 8-bit microcontrollers
 Advanced RISC architecture
 131 Powerful Instructions – Most Single-clock Cycle
Execution
 32 × 8 General Purpose Working Registers
 Fully Static Operation
 Up to 16 MIPS Throughput at 16MHz
 On-chip 2-cycle Multiplier

Features of AVR microcontrollers
 32Kbytes of In-System Self-programmable Flash
program memory
 1024Bytes EEPROM
 2Kbytes Internal SRAM
 Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
 Two 8-bit Timer/Counters with Separate Prescalers
and Compare Modes
 One 16-bit Timer/Counter with Separate Prescaler,
Compare Mode, and Capture Mode

 Real Time Counter with Separate Oscillator
 Four PWM Channels
 8-channel, 10-bit ADC
 Byte-oriented Two-wire Serial Interface
 Programmable Serial USART
 Master/Slave SPI Serial Interface
 Programmable Watchdog Timer with Separate On-
chip Oscillator
 On-chip Analog Comparator

 External and Internal Interrupt Sources
 21 interrupts including RESET
 32 Programmable I/O lines

Memory organization
 The AVR architecture has two main memory spaces,
the Data Memory and the Program Memory space.
 In addition, the ATmega32 features an EEPROM
Memory for data storage.

Data Memory
32 bytes
64 bytes
2048 bytes

Data Memory
 The lower 2144 Data Memory locations address the
Register File, the I/O Memory, and the internal data
SRAM.
 The first 32 locations address the Register File (32 × 8
General Purpose Working Registers).
 The next 64 locations address I/O Memory.
 The next 2048 locations address the internal data
SRAM.

Data Memory
 General Purpose Registers: The address locations
from $00 to $1F in the data memory are 32 general
purpose registers, each of 8-bit named as R0 to R31.
 I/O Memory: Memory locations from $20 to $5F is
used for I/O memory (SFRs). The I/O memory is
dedicated to specific functions such as status register,
timers, serial communication, I/O ports, ADC and so
on.
 The function of each I/O memory location is fixed by
the CPU designer at the time of design because it is
used to control the microcontroller or peripherals.

Data Memory
 The AVR I/O memory is made of 8-bit registers.
 All the AVRs have at least 64bytes of I/O memory
locations.
 This 64-byte section is called standard I/O memory.
 In AVRs with more than 32 I/O pins (Atmega64,
Atmega128, Atmega256) there is also an extended
I/O memory, which contains the registers for
controlling the extra ports and extra peripherals
 In other microcontrollers this I/O memory is called
as Special Function Registers (SFRs)

Data Memory
 Internal SRAM: It is used for storing data and
parameters by AVR programmers and C compilers
temporarily.
 Generally this is called as Scratch Pad.
 Each location in SRAM can be accessed directly by
its address, which is 8-bits wide.

Data Memory-EEPROM
 The AVR has an EEPROM memory (1Kb) that is used
for storing data.
 It does not lose its data even when power is OFF,
where as SRAM does.
 So, the EEPROM is used for storing data that should
rarely be changed and should not be lost when the
power is OFF, i.e, options and settings etc; whereas
the SRAM is used for storing data and parameters
that are changed frequently.

Program Memory
 The ATmega32 contains 32 Kbytes On-chip In-
System Reprogrammable Flash memory for
program storage.
 For software security, the Flash Program memory
space is divided into two sections,
 Boot Program section and
 Application Program section.

Program memory
 A code can be programmed into either the
Application Section or the Boot loader Section (BLS).
 The code programmed into the Application section
runs normally and is used for common applications,
whereas the code running in the BLS is provided with
some special features.
 The code running in the BLS section can execute Self
Programing Mode (SPM) instructions which are
blocked for the code running in the Application
section.

Program memory
 Using SPM instructions the code from the BLS can rewrite
the code in the application section or the code in the BLS
itself.
 The BLS section is normally used for storing the Boot-
loader code for the microcontroller.
 Boot-loaders are a code which executes when the
microcontroller in powered ON or RESET. It sets an
environment for the application code to execute, mainly
it have to perform a minimally :
 initialize the controller peripherals
 get the application (UART, SD card ...etc )
 load selected user application
 start the code (execute)

Program memory
 Usually the main reason to change the standard
boot-loader is to be able to change the application
and program the microcontroller without an external
programmer.
 Some boot-loaders can perform many other
functions . The Boot-Loader codes in microcontrollers
are actually very small and simple compared to the
Boot-Loaders in advanced devices like PC.

Boot loader size configuration

Program memory
 The Boot-Loader code can be used for
 initializing the peripherals in the microcontroller,
 initialize the devices connected to the microcontroller,
 select the application to load and execute from a
storage medium,
 load the selected application to the application section,
 jump to the application section and execute the
application.

AVR Family-Tiny & Special purpose

Block diagram of ATmega32 microcontroller

Joint Test Action Group (JTAG)
 The JTAG interface is a 4-wire Test Access Port (TAP)
controller that is in compliant with the IEEE 1149.1
standard, which can take control of the pins of all the
IC’s connected to this interface. The IEEE standard was
developed to enable a standard way to efficiently test
the circuit board connectivity (Boundary Scan) in 1990.
 The JTAG (Joint Test Action Group) development started
about 1985 as a method to test populated circuit boards
after manufacturing.
 The majority of manufacturing and field faults in circuit
boards were due to bad solder joints.
 JTAG was meant to provide a “pins-out” view from one
IC pad to another so all these faults could be discovered.

Joint Test Action Group (JTAG)
TMS- Test Mode Selection (Sampled at rising edge of TCK to decide the next state.
TCK- Test Clock (Synchronizes the internal state machine operations)
TDI- Test Data Input (Represents the data shifted into the device's test or programming logic.
It is sampled at the rising edge of TCK)
TDO- Test Data Output (Represents the data shifted out of the device's test or programming
logic and is valid on the falling edge of TCK)

On-Chip Debugging (OCD)
 An on-chip debug module is a system allowing a
developer to monitor and control execution on a
device from an external development platform,
usually through a device known as a debugger or debug
adapter.
 With an OCD system the application can be executed
whilst maintaining exact electrical and timing
characteristics in the target system, while being able
to stop execution conditionally or manually and inspect
program flow and memory.

Serial Peripheral Interface (SPI)
 Serial Peripheral Interface (SPI) is an interface bus
commonly used to send data between microcontrollers
and small peripherals such as shift registers, sensors,
and SD cards. It uses separate clock and data lines,
along with a select line to choose the device you wish to
communicate with.
 The SPI is a synchronous communication interface
specification used for short distance communication
primarily in embedded systems.
 This interface was developed by Motorola in mid 1980’s.
 SPI devices communicate in Full duplex mode using a
master-slave architecture with a single master.
 The SPI bus can operate with a single master device
and with one or more slave devices.

SCLK- Serial Clock signal from master to slave
MOSI- Master Output Slave Input
MISO- Master Input Slave Output
SS- Slave Select

 During each SPI clock cycle, a full duplex data
transmission occurs.
 If the communications involves multiple slaves, there
are two ways possible to connect the slaves
 The master should have number of Slave Select lines
equal to number of Slaves.
 Daisy chained connection using single Slave Select line
connecting all the slaves. (data will be sent continuously
to all the slaves and the first byte of data will end up in
last slave. This is typically used for output only situations.)
 Typical applications include Secure Digital cards and
Liquid Crystal Displays.

Two Wire Interface (TWI)
 I²C (Inter-Integrated Circuit), pronounced I-squared-
C, is a synchronous, multi-master, multi-
slave, packet switched, single ended, serial
computer bus invented in 1982 by Phillips
Semiconductor (now NXP Semiconductors).
 It is widely used for attaching lower-speed
peripheral ICs to processors and microcontroller in
short-distance, intra-board communication.
Alternatively I²C is spelled I2C (pronounced I-two-
C) or IIC (pronounced I-I-C).

Applications of TWI
 Accessing real time clocks
 Accessing low speed DACs and ADCs
 Changing contrast, hue and color balance settings in
monitors
 Changing sound volume in intelligent speakers
 Controlling small OLED or LCD displays
 Turning ON and turning OFF the power supply of
system components

Two Wire Interface (TWI)
 Features of Two Wire Interface
 More flexible than SPI
 Master and slave modes supported
 9-bit Address packet [ 7-bit slave address+1
read/write control bit (driven by master)+1
acknowledge bit (driven by addressed slave) ]
 9-bit Data packet [ One data byte plus an
acknowledge ]
 400khz data transfer speed
 Two wires, SCL (clock) and SDA (data)

Two Wire Interface (Optional slide)
 A TWI transmission consists of
 A Start condition
 An address packet consisting of
 Read/Write indication or Data Direction and
 Slave acknowledge
 One or more data packets
 A Stop condition
 A Start condition initiates a transmission by a master. Between
Start and Stop conditions, the bus is busy and no other masters
should try to initiate a transfer.
 A Start condition is signaled by a falling edge of SDA while
SCL is high.
 A Stop condition completes a transmission by a master. A Stop
condition is signaled by a rising edge of SDA while SCL is
high.

Two Wire Interface (Optional slide)
holding SDA low for
one clock cycle
logic zero the master performs write
operation with slave or if the data direction
bit is logic one then the master performs
read operation from slave. The data
direction bit is also known as Read/Write
Control bit

Watchdog Timer
 Watch dog timer is a special timer, which runs from
a separate on-chip watchdog oscillator of 1MHz
frequency.
 This timer can be enabled in any section of the
code and when enabled it ensure that a certain
number of instructions execute with a pre-defined
time-frame.
 This time-frame or time delay can be
configured/set using the registers of watchdog
timer.

Watchdog Timer
 In case the instructions are executed within the time-
frame, watchdog timer needs to be turned OFF and
the program execution continues.
 However, if the instructions fail to execute within this
time frame, the entire system reboots thus avoiding
any system crash or hang up.

AVR General purpose registers & ALU

Arithmetic and Logical Unit (ALU)
 Like in most of the microprocessors and
microcontrollers, the AVR microcontroller also has
ALU, the fundamental processing unit, which performs
the arithmetic and logical operations on the data
stored in general purpose registers.
 After the execution of these operations by the ALU
the result is again stored in these general purpose
register itself.
 As ATmega32 is an 8-bit microcontroller the ALU
used in this microcontroller can process 8-bit data at a
time to produce output.

Arithmetic and Logical Unit (ALU)
 The status of the previous arithmetic and logic
instruction is stored in a special function register
called SREG, Status Register.
 Based on the flag bits/status bits raised in this SREG,
the program flow can be manipulated which are
mostly program flow control instructions like,
conditional jump instructions.
 And in some cases the state of the status bit
particularly carry flag bit ‘C’ will be used in few
arithmetic instructions.

General Purpose registers
 These are the registers which occupy the initial 32
location of data memory from 0000H to 001FH.
 These register are 8-bit wide and are named as R0 to
R31.
 These general purpose registers are used to handle the
data which is used in a given application.
 In LDI & ADD instructions these general purpose
registers can be used as source and destination
operands.
 But, the registers from R16 to R31 can only be used as
destination operand, we cannot used R0 to R15 as
destination operand while handling immediate
values.

Status Register (SREG)
SREG 7 6 5 4 3 2 1 0
0×3F
I T H S V N Z C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
The Status Register (SREG) is an 8-bit register which contains information
about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform
conditional operations. The Status Register is updated after all ALU
operations.

Architecture of
AVR microcontroller

1-AVR Introduction to Atmega32 good .pdf

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