What the power is going on? Part 1 - Intro

Have you ever wondered how your phone can perform so many different functions or operations at the click of an icon and yet lasts hours to a full day without having to charge the battery? Do you know how a pill camera used in Gastroenterology can transmit real time images of your gut health to your doctor lasting over 8 hours without having to recharge its battery? All of these things and beyond, are made possible because of low power designs VLSI engineers develop.

With the growing use of integrated circuits in almost every industrial segment, power consumption of circuits within large VLSI designs is an important problem to address. While we continue to enjoy the benefits of many breakthroughs in circuits that deliver high throughputs these days at very small voltages, packing designs with so many switching circuits continues to pose a complicated challenge for VLSI engineers to solve. But how did we get here, where seeing low power chips is taken for granted nowadays? The answer continues to lie in efficient power techniques developed in the last two decades specifically. So, let me start with a basic introduction that can help anyone to understand how low power circuit architectures help reduce overall power consumption in large SoC designs.

Controlling power demand in high performance designs is a big part of closing low power designs successfully for EM/IR and timing/delayCal sign-off. Having a good understanding on all of the power consumption sources at device level to cell level, and from cell level to the domain level and design level, is an important part of the low power design. Let me use a an easy circuit to summarize various current sources that contribute to the total power consumption in CMOS devices.

Fig 1(a). and Fig 1(b)., show the CMOS inverter circuit. Fig 1(a) shows all the components of switching power. Fig 1(b) shows the sources of leakage power. So, from Fig 1(a), we see two types of power consumption: 

(1.1) switching power due to the charging (blue arrow) and discharging (green arrow) of the load capacitance whenever the signal toggles. This power is a function of switching activity (AF), load capacitance (l_cap), operating voltage (V), and clock frequency (F): 

 P_switching = AF x l_cap x V^2 x F        

(1.2) internal power due to the instantaneous short circuit (red arrow) between the pull-up network and pull-down network. This power component is a function of the duration of the short-circuit (TSC), operating voltage (V), switching current (ISC), and clock frequency (F):

 P_internal = TSC x V x ISC x F         

(1.3) leakage power from gate (labeled ‘GL’), drain junction leakage (labeled DL), and leakage due to MOSFETs operating weak inversion (labeled as SL). Let us assume our total leakage current is ILKG. So, this power component is a function of operating voltage (V) and total leakage current (ILKG):

 P_leakage = V x ILKG         

The total power is the sum of (1.1), (1.2), and (1.3).

We have left out a very important and a big item for now--what is this switching activity factor we used in (1.1)? This one requires its own article and therefore, I will discuss this in future.

If you want to read up on power components of the total power consumption of a CMOS circuit, then [1] is a great reference. Also, if you want to know more details on leakage power components [2] is a must-read (especially chapters on 3 terminal and 4 terminal MOSFETs).

If our goal is to design a high performance and low power consumption SoC, we have to have a good architecture level planning for all the SOC blocks. For example, in our highly simplified Fig 2., not every block has to be always on as that will result in a large power consumption in the chip.

By carefully studying the SoC architecture, we can determine that some blocks must retain the state for subsequent operations, some blocks or cells must be always on, some blocks or cells can be shut-off or woken up in future functional cycles of the SoC. Luckily, EDA tools also are getting smarter in assisting the designers develop efficient low power designs. So, how is it possible that we can turn off a part of our design, use multiple different supply voltages for multiple areas of the SoC design, have separate voltage islands, or put some switching circuits in sleep mode? It is possible because we have a variety of library cells (basic building blocks in digital designs) developed to assist in solving power challenges. Various techniques such as clock gating, voltage scaling, power gating, design partitioning, using devices with higher threshold voltages, etc., are commonly used to develop a low power SoC.

For this discussion though, I will assume that the design is already partitioned into regions where each region operates at a certain voltage value. Further, I will assume the design has certain functional blocks operating in specific modes (sleep, isolation, retention, etc.). With these assumptions, here are the cell types and their specific role in low power design:

Clock gating cells: Enables reducing the power consumption in the clock network by turning off the clocks when they do not need to be on.

Header switches: Used in switching the switched side of a VDDn power networks of the power grid.

Footer switches: Used to switch the switched side of the VSSn ground networks of the power grid.

Level Shifters: Used to switch up the voltage value (from a lower voltage value) or switch down the voltage value (from a higher voltage value).

Always-on cells: Used to keep certain regions or blocks on even if other parts of the SoC are in sleep mode.

State retention cells: Used to retain the logic states when the blocks are powered down such that the previous states (or retained states) are available when these powered down blocks wake up. There is actually a lot of ongoing research in this area that I will discuss in a subsequent article.

Domain or net isolation cells: Used to isolate shutdown domains from active domains or simply isolate power domains.

In my subsequent articles, I will discuss each of these circuits and their use from the perspective of logic, circuit analysis, some important background math, and their role in low power SoC/VLSI design since these cells are critical for a good EM/IR sign-off. If you want to know how Voltus and Voltus Insight treat low power designs guaranteeing excellent accuracy between flat analysis Vs. hierarchical analysis, reach out to me and I will happily help. Feel free to repost or use this article for your own needs.

References

[1] Rabaey, J.M., “Digital Integrated Circuits: A Design Perspective”, Prentice Hall, Upper Saddle River, NJ.

[2] Tsividis, Y., “Operation and Modeling of the MOS Transistor”, 2nd Edition, WCB/McGraw-Hill, 1999, New York, NY.

[3] Hennessy, J.L. and Patterson, D.A., “Computer Architecture: A Quantitative Approach”, 6th Edition, Morgan Kaufmann Publishers., San Francisco, CA.