Transaction Layer in PCIe Part -1: Overview and TLP

The Transaction Layer (TL) in PCIe (Peripheral Component Interconnect Express) is the topmost layer responsible for managing transaction-level communication between devices. It handles packetization, flow control, error detection, and routing. 

Overview of the Transaction Layer (TL)

The TL sits between the device's core logic (application layer) and the Data Link Layer (DLL). Its primary roles include:

1. Packetization: Assembling and disassembling Transaction Layer Packets (TLPs).
2. Data Exchange: Translating application-layer read/write requests into TLPs for transmission.
3. Error Detection: Checking for End-to-End CRC (ECRC) errors.
4. Flow Control: Managing buffer credits to prevent overflow.
5. Address Space Support: Handling Memory, I/O, Configuration, and Message transactions.

Transaction Layer Packet (TLP) Structure

A TLP consists of:

1. Header (3 or 4 Double Words (DW)): Format Field: Determines header size and payload presence: Bit 0: 0 = 3DW header, 1 = 4DW header. Bit 1: 0 = No payload, 1 = Payload included. Type Field: Specifies TLP type (e.g., Memory Read, Configuration Write). Address/Request Details: Varies by TLP type (e.g., 32-bit vs. 64-bit memory addresses).
2. Data Payload (0–1024 DW, configurable).
3. TLP Digest (Optional): ECRC for error detection.

Types of TLPs

TLPs are categorized into three types based on transaction requirements:

1. Posted TLPs

• No response required (e.g., Memory Writes, Messages).
• Examples: Memory Write TLP: Transfers data to a memory address. Message TLP: Used for interrupts, power management, or vendor-specific commands.

2. Non-Posted TLPs

• Require a Completion TLP (response).
• Examples: Memory Read: Requests data from a memory address. I/O Read/Write: Accesses legacy I/O space (limited to 32-bit, often 16-bit). Configuration Read/Write: Accesses PCIe configuration space (registers).

3. Completion TLPs

• Response to Non-Posted TLPs (e.g., returning read data).
• Fields: Completer ID: Identifies the responding device. Status: Indicates success/failure (e.g., "Unsupported Request"). Data Payload: For read completions.

TLP Header Formats

Each TLP type has a unique header structure:

Memory Request TLP

• 3DW Header: 32-bit memory address.
• 4DW Header: 64-bit memory address.
• Key Fields: Address: Target memory location. Length: Data payload size (in DW). First/Last DW Byte Enable: Controls byte granularity.

Configuration Request TLP

• Accesses PCIe configuration space (device registers).
• Key Fields: Bus/Device/Function (BDF): Identifies the target device. Register Number: Specifies the register offset.

I/O Request TLP

• Always uses a 4DW header but supports only 1DW payload (32-bit data).
• Limited to legacy systems (rarely used in modern PCIe).

Message Request TLP

• 4DW header with a Message Code field (e.g., interrupt, error signaling).
• Bypasses traditional address spaces.

Completion TLP

• Matches the original request using Requester ID and Tag.
• Includes Completion Status and data (for reads).

TLP Flow in PCIe

Transmitter:

• TL forms TLP (header, payload, ECRC if enabled).
• Passes to DLL, which adds sequence number and LCRC.
• PL adds STP (start), END, and serializes data.

Receiver:

• PL deserializes, removes STP/END.
• DLL verifies LCRC, sequence number, and sends TLP to TL.
• TL checks ECRC, extracts data, and delivers to core logic.

Flow Control in the Transaction Layer

• Credit-Based Mechanism: The receiver reports buffer availability (credits) via Data Link Layer Packets (DLLPs). Virtual Channels (VCs): Up to 8 independent channels for prioritizing traffic (e.g., high-priority vs. bulk data).
• Process:

• Transmitter checks receiver credits.
• Credits are updated via DLLPs exchanged between DLL layers.
• TLPs are sent only if credits are available.

Generic Header Fields:

• Format (Fmt): header size is 3 DW or 4 DW, payload presence.
• Type: Encodes the transaction type.
• TC (Traffic Class): Priority level (0–7) for QoS.
• Attr (Attributes): Controls ordering (Relaxed, ID-Based) and cache behavior (No Snoop).
• TH (TLP Processing Hints): 1 bit.
• TD (TLP Digest): 1 bit (ECRC presence).
• EP (Poisoned Data): 1 bit: Marks corrupted data (e.g., for error handling).
• Length: 10 bits (payload size in DW).
• Requester ID: Bus/Device/Function (BDF) of the transaction initiator.
• Tag: Unique ID for tracking non-posted transactions.
• Completion ID: Bus/Device/Function (BDF) of the transaction completer.
• Transaction ID:  The combination of the Requester ID and the Tag field of the TLP is termed as Transaction ID of the TLP.