Timing Constraints

1.      create_clock

Defines the primary clock for the design with a specified period.

Example:

create_clock -name clk -period 10 [get_ports clk]        

2.      create_generated_clock

Defines a clock that is derived from another clock (e.g., clock divider or multiplier).

Example:

create_generated_clock -name gen_clk -source [get_ports clk] -divide_by 2 [get_pins U1/Q]        

3.      set_clock_groups

Specifies mutually exclusive clocks to avoid false timing violations between them.

Example:

set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2]        

4.      set_clock_latency

Specifies the propagation delay of the clock signal from the source to the sequential elements.

Example:

set_clock_latency 2 [get_clocks clk]        

5.      set_clock_transition

Sets a limit on the maximum transition time (slew) for a clock signal.

Example:

set_clock_transition 0.5 [get_clocks clk]        

6.      set_clock_uncertainty

Defines the clock uncertainty (jitter or skew) to account for variations in the clock network.

Example:

set_clock_uncertainty 0.2 [get_clocks clk]        

7.      set_clock_sense

Defines the polarity of the clock (rising or falling edge).

Example:

set_clock_sense -positive [get_clocks clk]        

8.      set_propagated_clock

Indicates that the clock is propagated through the clock network (consider real clock latency).

Example:

set_propagated_clock [get_clocks clk]        

9.      set_input_delay

Defines the time taken for signals to arrive from external sources to input ports.

Example:

set_input_delay 2 -clock [get_clocks clk] [get_ports data_in]        

10.   set_output_delay

Specifies the time required for signals to propagate from output ports to external destinations.

Example:

set_output_delay 3 -clock [get_clocks clk] [get_ports data_out]        

11.   set_clock_gating_check

Sets conditions for clock gating checks (like minimum gating width).

Example:

set_clock_gating_check -setup 0.5 -hold 0.2 [get_clocks clk]        

12.   set_ideal_latency

Specifies an ideal (estimated) clock latency instead of actual propagation delay.

Example:

set_ideal_latency 1.5 [get_clocks clk]        

13.   set_ideal_network

Defines a clock network as ideal, meaning its effects are not considered during synthesis.

Example:

set_ideal_network [get_clocks clk]        

14.   set_ideal_transition

Sets an ideal transition time for clock signals, bypassing slew analysis.

Example:

set_ideal_transition [get_clocks clk]        

15.   set_max_time_borrow

Specifies the maximum allowable time borrowing between clocked elements in time-borrowing designs.

Example:

set_max_time_borrow 2 [get_clocks clk]        

16.   set_resistance

Specifies the resistance for nets during timing analysis, typically for post-layout extraction.

Example:

set_resistance 50 [get_nets net1]        

17.   set_timing_derate

Adjusts timing calculations by applying a scaling factor to delays for pessimism or optimism.

Example:

set_timing_derate -early 0.9 -late 1.1        

18.   set_data_check

Defines a timing check for data paths, such as setup or hold requirements.

Example:

set_data_check -setup 1.0 -hold 0.5 [get_clocks clk]        

19.   group_path

Groups multiple timing paths together for reporting or optimization purposes.

Example:

group_path -name critical_paths -from [get_ports data_in] -to [get_ports data_out]        

20.   set_drive

Specifies the drive strength for input ports or nets.

Example:

set_drive 2 [get_ports clk]        

21.   set_load

Defines the capacitive load for output ports or internal nets.

Example:

set_load 0.1 [get_ports data_out]        

22.   set_input_transition

Specifies the transition time (slew) for input signals.

Example:

set_input_transition 0.2 [get_ports data_in]        

23.   set_fanout_load

Specifies the maximum fanout for cells or nets to ensure excessive fanout does not degrade timing.

Example:

set_fanout_load 4 [get_ports clk]        

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