Optimizing SRAM IP for Yield and Reliability
My IC design career started out with DRAM at Intel, and included SRAM embedded in GPUs, so I recall some common questions that face memory IP designers even today, like:
- Does reading a bit flip the stored data?
- Can I write both 0 and 1 into every cell?
- Will read access times be met?
- While lowering the supply voltage does the cell data retain?
- How does my memory perform across variation?