My first Cortex-M in an Artix/Spartan

Sharing my initial Cortex-M experience in a Spartan/Artix Device:

After downloading the core from ARM (a free account with ARM is needed) and pointing the repositories of Vivado and SDK to the extracted archive - the new M1 core is directly accessible from the IP catalog. It comes with an integrated AXI Bridge (from AHB/APB) so that all existing Xilinx AXI-IP can directly be connected and the wonderful connect assistance helps to build a working system in minutes.

You notice in the block diagram that no memory is visible. (unlike in a Microblaze Design) where a BRAM controller and BRAM-IP is needed to create the instruction and data memories. The ARM core simply can be configured with your choice of memory space and then creates these as TCM (tightly coupled Memory) inside the core. This means no waitstate access and much higher performance that would be expected from a classic M0/M0+ MCU from ST or NXP.

It consumes 2267 LUT6 (28%) and 1956FF (12%) which means approx. 3-4kLE, in the same range than a typical Microblaze. By default a 100Mhz clock wizard and a reset logic are generated as soon as block automation is run. In a (very small) 7A12 it consumes ca. 30% of the logic - in a midrange 7S50 it would amount to >10% leaving >90% of logic free for other use.

Software Development can be done with the Xilinx SDK (free in Webpack Edition) and/or with ARM KEIL or other Cortex-M Tools.

The benefit of using SDK is that all works very seamlessly together and the SAME SDK can be used to write software for A9 / A53 (ZYNQ), A72 (VERSAL), Cortex-M, Cortex-R (MPSoC) or Microblaze. All those cores included and supported in the same Eclipse IDE means higher effectiveness and less time to market.

ARM provides a series of video tutorials, to help with some settings that are required to make KEIL work seamlessly with the bitstream generation of Vivado. Typically you would generate the bitstream only once as long as no hardware changes occured (like in the Xilinx toolchain) and iterate software changes by merging new .elf/.hex compiles with the existing bitstream.