Design of universal programmable hardware for embedded Applications
A Smart hardware design for programmable embedded Applications
The Electronic Hardware Design Approach has been evolving constantly to address the needs of emerging embedded applications. Over a period of time, Hardware Design has transformed from a customized approach to a flexible and programmable approach to use the same hardware for different applications as per need by programming the different applications for execution in real-time. This has been a challenging task to optimize the cost and computational resources along with design architecture. Time to market has always been a pressure for companies.
A cost-effective design approach of Hardware is presented here for moderate programmable embedded applications.
ASP Analog Signal Processor
ADC Analog to Digital Converter
DAC Digital to Analog Converter
DSP Digital Signal processor
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BITS Built-in test suites
Hardware Accelerator Implemented in CPLD/ FPGA
The computational power of the DSP is to be selected as per the need in view of the cost and performance. The resolution of the digital signal converted from Analog and the sampling rate of the ADC will vary from application to application. With the advancement of mixed-signal design technology, it is recommended to use a minimum of 16-bit ADC with a few hundred kilo sampling to cater for the need to low to moderate applications.
The cost of the Hardware Accelerator (CPLD/ FPGA) will be defined mostly by the number of gates and the clock cycle it supports.
For Signal Conditioning, Analog Signal processors have recently been available which can cater for the needs of amplification/ attenuation, filtering, level shifting…etc before the signal is made properly to digitize through an Analog to an analogue-to-digital converter. Thanks to the simulation tools, ASP behaviour can now be predicted in simulation just like DSP.
Earlier in Electronic hardware design, a microcontroller and a DSP were used separately for control functions and signal processing applications respectively. Now the new generation of DSPs have combined the capabilities of both RISC and DSP architecture in the same chip obviating the need of a separate microcontroller for controlling the peripherals. These new generation DSP chips have also inbuilt physical layers of Digital I/O like USB, SPI, CAN..etc which makes life easy for a hardware designer. The enormous computation provided in the single DSP chip also makes the task of a real-time Operating system simpler.
The key design issue in designing smart hardware for universal embedded applications is defining the parameters like instruction cycle time of the Processor, access time of RAM and of course the right selection of Hardware Accelerator capabilities. These tasks can not be simply defined optimally by a hardware designer who does not have the knowledge of developing and porting applications for real-time execution. Designing the Buit-in Test suites has sometimes been more challenging than designing the algorithms for a particular task, as any corner case bug in the hardware will compound the problem of debugging. The design approach here has been optimized in view of the available components in the market and in view of easy hardware-software co-partitioning.
Surya Kumar (SK) Singh Chief Scientist, eAge Technologies Pvt Ltd., Bangalore