ASIC Flow in VLSI

Designing an ASIC is a meticulous process involving several stages, each contributing to creating a highly specialized chip. The key phases of ASIC design include:

Specification and requirements:

This is the first stage of ASIC design flow, which involves defining the specifications and requirements to start the design process. It consists gathering input from pertinent stakeholders and translating the overarching product specifications into detailed technical specifications. Expected outputs, performance objectives, power consumption targets, and other essential parameters must be clearly outlined.

Architecture design:

Once the specifications are in place, the architecture of the ASIC is designed. This involves determining the overall structure, the arrangement of functional blocks, and the interconnections between these blocks. Engineers must brainstorm many possible ideas and select the ideal approach by carefully considering performance implications, technical feasibility, and hardware resources while keeping the overall cost within the assigned budget.

RTL design:

Register-transfer level (RTL) design involves describing the functionality of the ASIC using a hardware description language (HDL). This phase serves as a bridge between the abstract architectural design and the physical implementation.

Verification:

Verification ensures that the ASIC meets the specified requirements by testing and simulating the design on the test bench. This stage is critical in identifying and rectifying any design flaws or issues.

Synthesis and implementation:  

During synthesis, RTL code is converted into a gate-level netlist, representing the ASIC's physical implementation. This netlist is translated into a layout, and the physical design is optimized for power consumption, speed, and area.

Static Timing Analysis (STA):

Analyze the timing requirements of the design to ensure that all signals meet setup and hold time constraints. STA identifies critical paths and optimizes timing through techniques like buffer insertion and pipeline balancing.

Chip Partitioning:

This is the stage wherein the engineer follows the ASIC design layout requirement and specification to create its structure using EDA tools the engineers partition the entire ASIC into multiple functional blocks (hierarchical modules), while keeping in mind ASIC’s best performance, technical feasibility, and resource allocation in terms of area, power, cost and time.

Design for Test (DFT) Insertion:

ASIC design is complex enough at different stages of the design cycle. With the ongoing trend of lower technology nodes, Due to these factors, new models and techniques are introduced to high-quality testing.

• Scan path insertion: A methodology of linking all registers elements into one long shift register (scan path). This can help to check small parts of design instead of the whole design in one go.
• Memory BIST (built-in Self-Test): In the lower technology node, chip memory requires lower area and fast access time. MBIST is a device which is used to check RAMs. It is a comprehensive solution to memory testing errors and self-repair proficiencies.
• ATPG (automatic test pattern generation): ATPG is a method of creating test vectors / sequential input patterns to check the design for faults generated within various elements of a circuit.

Floor Planning:

In physical design, the first step in RTL-to-GDSII design is floorplanning. It is the process of placing blocks in the chip. It includes: block placement, design portioning, pin placement, and power optimization.

Floorplan determines the size of the chip, places the gates and connects them with wires. While connecting, engineers take care of wire length, and functionality which will ensure signals will not interfere with nearby elements.

Placement:

Placement is the process of placing standard cells in row. A poor placement requires larger area and also degrades performance. Various factors, like the timing requirement, the net lengths and hence the connections of cells, power dissipation should be taken care. It removes timing violation.

Clock tree synthesis:

Clock tree synthesis is a process of building the clock tree and meeting the defined timing, area and power requirements. It helps in providing the clock connection to the clock pin of a sequential element in the required time and area, with low power consumption.

In order to avoid high power consumption, increase in delays and a huge number of transitions, certain structures can be used for optimizing CTS structure such as Mesh Structure, H-Tree Structure, X-Tree Structure, Fishbone Structure and Hybrid structure.

With the help of these structures, each flop in the clock tree gets the clock connection. During the optimization, tools insert the buffer to build the CTS structure. Different clock structures will build the clock tree with a minimum buffer insertion and lower power consumption of chips.

Routing:

1. Global Routing: Calculates estimated values for each net by the delays of fan-out of wire. Global routing is mainly divided into line routing and maze routing.
2. Detailed Routing: In detailed routing, the actual delays of wire is calculated by various optimization methods like timing optimization, clock tree synthesis, etc.

As we are moving towards a lower technology node, engineers face complex design challenges with the need for implanting millions of gates in a small area. In order to make this ASIC design routable, placement density range needs to be followed for better QoR. Placement density analysis is an important parameter to get better outcomes with less number of iterations.

Final Verification (Physical Verification):

After routing, ASIC design layout undergoes three steps of physical verification, known as signoff checks. This stage helps to check whether the layout working the way it was designed to. The following checks are followed to avoid any errors just before the tapeout:

1. Layout vs Schematic (LVS) is a process of checking that the geometry/layout matches the schematic/netlist.
2. Design Rule Check (DRC) is the process of checking that the geometry in the GDS file follows the rules given by the foundry.
3. Logical Equivalence Check (LVC) is the process of equivalence check between pre and post design layout.

Timing Closure:

Iterate through synthesis, placement, and routing steps to achieve timing closure, ensuring that all timing constraints are met. Timing closure involves tweaking design parameters, adding buffers, or redesigning critical paths if necessary.

GDS II – Graphical Data Stream Information Interchange:

In the last stage of the tapeout, the engineer performs wafer processing, packaging, testing, verification and delivery to the physical IC. GDSII is the file produced and used by the semiconductor foundries to fabricate the silicon and handled to client.