ASIC Clocks

Every ASIC device requires clocking initialization sequence, enabling clock to start and reset to be propagated through to all parts of the logic. The design of an ASIC clocking and reset logic is a sensitive task. Different PLLs require special attention in the initialization sequence and a design that is not robust enough to handle the situation may result in a device where the clocks cannot be used.

Review and define the following

•      Clocking requirements, specific PLL details

•      Overall power-up sequence and software/hardware partition

•      Reset requirements

•      DFT clocking requirements

•      Definition of required configuration and source of information

•      Definition of initial solution

•      Define timing requirements, clock balancing strategy

•      Document clocking instructions for physical design

•      Modifications and late changes if needed

•      Gate level simulation support for power-up test

•      Design of a robust and low risk clocking and reset structure is essential for first time ASIC success.

The clocking and reset initialization sequence is different from other purely logical parts as it handles slow signals external to the device, an analog PLL and depends on the sequencing of the device power rails, external clock generators and I/O pads. In many cases, testability and initialization backup logic is also included, further complicating this delicate logic.sensitive logic is responsible for initializing the main device PLL and releases from reset the portions of the design that are required for booting the device.

The clocks and reset block includes multiple clock domain, specific layout requirements, externally driven signals as well as internal controls and other complications. In many cases multiple PLLs need to be initialized and a specific power-up order needs to be followed using a sequence that involves both hardware and software. The definition of the device reset sequence and reset distribution method is essential for securing a known state of all device IPs sequential elements. The clocks and reset block affects the device DFT, timing closure, ATE testing, bring-up and validation and a wide perspective is required to enable integration of all requirements into a robust design

      Digital ASICs must be designed to be synchronous when possible. This must be considered, when VHDL for synthesis is written.

 The  main benefits of synchronous design are:

     Timing problems are avoided. Only the propagation of signals   to the next register during one clock cycle must be verified.

   Most of the problems with hazards are avoided.

    The X-states and glitches in gated and multiplexed clocks are avoided.

     It is easier to test a synchronous circuit than an asynchronous one.

     Static timing analysis is possible.

     Partition the design so that all the logic in a single module uses a single clock and a single reset.

Isolating clock and reset generation logic in a separate module allows the other modules to use the standard timing analysis and scan insertion techniques. It also makes it easier to develop specific test strategies for the clock/reset generation logic.

Avoid gated clocks

Clock gating circuits tend to be technology specific and timing dependent. Improper timing of a gated clock can generate a false clock or glitch, causing a flip-flop to clock in the wrong data. Also,the skew of different local clocks can cause hold time violations. Gated clocks also cause limited testability because the logic clocked by a gated clock cannot be made part of a scan chain. If your design requires gated clocks, use preferably vendor provided

Avoid internally generated resets

Make sure your registers are controlled only by a single reset signal.

Avoid internally generated, conditional resets if possible. Generally,all the registers in the macro should be reset at the same time. Thisapproach makes analysis and design much simpler and easier. If conditional reset is required, create a separate signal for the resetsignal, and isolate this in a separate module. This approach results inmore readable code and improves synthesis results