Kulwant Singh’s Post

𝙑𝙀𝙍𝙄𝙁𝙄𝘾𝘼𝙏𝙄𝙊𝙉 𝘿𝙄𝘼𝙍𝙄𝙀𝙎 #6 📖 📒 📓 I asked Stefan Minić, one of our bright junior verification engineers here at Vtool - Smart Verification, who works in our office in Niš, what part of IP verification he loves the most. "𝑨𝒔 𝒔𝒐𝒎𝒆𝒐𝒏𝒆 𝒘𝒉𝒐 𝒉𝒂𝒔 𝒔𝒑𝒆𝒏𝒕 𝒒𝒖𝒊𝒕𝒆 𝒂 𝒃𝒊𝒕 𝒐𝒇 𝒕𝒊𝒎𝒆 𝒐𝒏 𝑰𝑷 𝒍𝒆𝒗𝒆𝒍 𝒗𝒆𝒓𝒊𝒇𝒊𝒄𝒂𝒕𝒊𝒐𝒏, 𝒕𝒉𝒆 𝒕𝒉𝒊𝒏𝒈 𝒕𝒉𝒂𝒕 𝑰 𝒍𝒐𝒗𝒆 𝒕𝒉𝒆 𝒎𝒐𝒔𝒕 𝒂𝒃𝒐𝒖𝒕 𝒊𝒕 𝒊𝒔 𝒕𝒉𝒆 𝒐𝒑𝒑𝒐𝒓𝒕𝒖𝒏𝒊𝒕𝒚 𝒕𝒐 𝒅𝒊𝒗𝒆 𝒅𝒆𝒆𝒑 𝒊𝒏𝒕𝒐 𝒕𝒉𝒆 𝒅𝒆𝒔𝒊𝒈𝒏'𝒔 𝒊𝒏𝒏𝒆𝒓 𝒘𝒐𝒓𝒌𝒊𝒏𝒈𝒔. 𝑻𝒉𝒊𝒔 𝒊𝒏𝒗𝒐𝒍𝒗𝒆𝒔 𝒕𝒆𝒔𝒕𝒊𝒏𝒈 𝒆𝒗𝒆𝒓𝒚 𝒔𝒊𝒏𝒈𝒍𝒆 𝒇𝒆𝒂𝒕𝒖𝒓𝒆 𝒂𝒏𝒅 𝒍𝒊𝒏𝒆 𝒐𝒇 𝒄𝒐𝒅𝒆 𝒂𝒏𝒅 𝒊𝒅𝒆𝒏𝒕𝒊𝒇𝒚𝒊𝒏𝒈 𝒂𝒏𝒅 𝒊𝒎𝒑𝒍𝒆𝒎𝒆𝒏𝒕𝒊𝒏𝒈 𝒔𝒄𝒆𝒏𝒂𝒓𝒊𝒐𝒔 𝒇𝒐𝒓 𝒆𝒗𝒆𝒓𝒚 𝒄𝒐𝒓𝒏𝒆𝒓 𝒄𝒂𝒔𝒆. 𝑨𝒏𝒅 𝒅𝒐𝒏'𝒕 𝒈𝒆𝒕 𝒎𝒆 𝒔𝒕𝒂𝒓𝒕𝒆𝒅 𝒐𝒏 𝒕𝒉𝒆 𝒔𝒂𝒕𝒊𝒔𝒇𝒂𝒄𝒕𝒊𝒐𝒏 𝒐𝒇 𝒔𝒆𝒆𝒊𝒏𝒈 𝒂 𝒅𝒆𝒔𝒊𝒈𝒏 𝒄𝒐𝒎𝒆 𝒕𝒐𝒈𝒆𝒕𝒉𝒆𝒓 𝒂𝒔 𝒊𝒕 𝒑𝒂𝒔𝒔𝒆𝒔 𝒕𝒉𝒓𝒐𝒖𝒈𝒉 𝒕𝒉𝒆 𝒗𝒆𝒓𝒊𝒇𝒊𝒄𝒂𝒕𝒊𝒐𝒏 𝒑𝒓𝒐𝒄𝒆𝒔𝒔. 𝑰𝒏 𝒇𝒂𝒄𝒕, 𝒕𝒉𝒆 𝒄𝒐𝒎𝒑𝒍𝒆𝒙𝒊𝒕𝒚 𝒐𝒇 𝒕𝒉𝒆 𝒑𝒓𝒐𝒄𝒆𝒔𝒔 𝒐𝒏𝒍𝒚 𝒂𝒅𝒅𝒔 𝒕𝒐 𝒕𝒉𝒆 𝒔𝒆𝒏𝒔𝒆 𝒐𝒇 𝒂𝒄𝒄𝒐𝒎𝒑𝒍𝒊𝒔𝒉𝒎𝒆𝒏𝒕 𝒘𝒉𝒆𝒏 𝒕𝒉𝒆 𝒋𝒐𝒃 𝒊𝒔 𝒅𝒐𝒏𝒆." Stay tuned for more stories to come. #verificationengineer #diaries #verification #bestjobever #stories ---------------------------------------- In this series, I am asking verification engineers about various aspects of their jobs. My hope is that their stories will inspire more people to truly appreciate how the job of verification engineer is interesting, challenging, and at the end of the day, very fulfilling.

#urgenthiring #VLSI #semiconductor #immediate Hi All, #hiring for #designverification #engineers at #Noida Exp: 5 to 8 years Design Verification, SV-UVM, AXI Protocols, Working in any high speed protocol is a plus do share your cv at manohar@shellinfotech.com #designverification #verification #SV #UVM #AXIprotocols #protocols #fulltime #immediatehiring

𝐄𝐱𝐜𝐢𝐭𝐞𝐝 𝐭𝐨 𝐣𝐨𝐢𝐧 𝐙𝐞𝐫𝐨 𝐃𝐚𝐲 𝐋𝐚𝐛 𝐟𝐨𝐫 𝐚 𝐭𝐚𝐥𝐤 𝐨𝐧 "𝐎𝐩𝐞𝐧-𝐒𝐨𝐮𝐫𝐜𝐞, 𝐂𝐨𝐦𝐦𝐞𝐫𝐜𝐢𝐚𝐥-𝐆𝐫𝐚𝐝𝐞 𝐑𝐈𝐒𝐂-𝐕 𝐈𝐎𝐌𝐌𝐔 𝐈𝐏 𝐰𝐢𝐭𝐡 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧" 𝐚𝐭 𝐭𝐡𝐞 RISC-V International 𝐒𝐮𝐦𝐦𝐢𝐭 𝐍𝐨𝐫𝐭𝐡 𝐀𝐦𝐞𝐫𝐢𝐜𝐚. In this session, we will discuss the verification methods 10xEngineers used to verify the IP. We utilized both UVM-based and formal verification methodologies to verify the IP. The verification plan has so far achieved 85% of the coverage targets. During this process, 10xEngineers identified several RTL bugs and design issues, using both functional and formal verification techniques, which have been addressed through collaborative efforts. 👉Find about 10xEngineers here: https://10xengineers.ai/ #RISCVSummit #RISCVEverywhere

#Hiring #Design_Verification_Engineer Must have skill :- #SV #UVM Exp :- 4+ Yrs Location :- #Bangalore 📩 radha.mishra1131@cientra.com #Like_comment_share_refer #DesignVerification #DV #SV #UVM #SystemVerilog

#DV-IP,#DV-SOC,#SV,#UVM,#OVM,#DDR,#VERILOG,#PCIE,#JOB OPENINGS,#JOB OPPOURTUNITY .

#DV-IP,#DV-SOC,#SV,#UVM,#OVM,#DDR,#VERILOG,#PCIE,#JOB OPENINGS,#JOB OPPOURTUNITY .

Verification

#Fundamentalsofverification As Designs are getting complex day-by-day, design-by-design and product-by-product, Verification also became a challenging task. These are different flows, methodologies and practices across industry but intention is same i.e. "Confidence of Zero defect design". To achieve it, fundamentals should be clear and deeply understood.. and it's not an easy task. One who is aspiring to be a Verification Expert, should have these technical knowhow -- 1. Testbench Architecture: To generate stimulus and observe the outputs. 2. Design understanding: Either IP or Integrated subsystem or Complete SoC or Chiplet 3. Measurement criteria for Design correctness: Functional coverage, Code coverage, Assertion coverage, Protocol checks coverage etc.. Here at #allaboutverification, we are trying to help aspiring Verification experts to redefine the learning curve or refresh the concepts.

Verification