Deven Hegade Patil’s Post

View profile for Deven Hegade Patil

Pre-Final year student at Indian Institute of Technology Bhubaneswar (IIT Bhubaneswar)

New Year, New Achievement, New Energy! 🌟 I am thrilled to share that two of our papers have been accepted for presentation at the prestigious 9th IEEE Electron Device Technology and Manufacturing (EDTM'25) conference held in Hong Kong, China this year! 🎉 1️⃣ "A Novel De-Mirroring Approach for Bias-dependent Capacitance Extraction in Nanosheet FET using Conformal Mapping" 2️⃣ "Self-heating and Process Induced Performance Barrier on Complementary Field Effect Transistor: A Reliability Perspective" As the first author of the first paper, I am especially proud of this work, where we proposed a novel de-mirroring approach for bias-dependent capacitance extraction in Nanosheet FETs (NSFETs). Our innovative method addresses the limitations of traditional mirroring techniques and achieves improved accuracy in capacitance modeling. I am grateful to my mentor Dr. Navjeet Bagga and Prof. Sudeb Dasgupta sir for their valuable guidance during this work.  I would also thank to my senior Sandeep Kumar, Dr. Sunil Rathore sir for thier continuous support during this time. Through this journey, I explored and gained expertise in: 🔹 Advanced Semiconductor Device Modeling: Developing and validating models for bias-dependent capacitance in NSFETs. 🔹 Analytical Techniques: Leveraging conformal mapping and elliptical integration to address complex capacitive networks. 🔹 Bridging Theory and Practice: Translating theoretical concepts into practical solutions for real-world challenges in nanoscale device design. 🔹 Performance Optimization: Understanding the impact of device parameters like gate length, extension regions, and parasitic capacitances on overall performance. Here’s to a bright and innovative 2025! ✨ #Research  #EDTM'25  #IITBhubaneswar  #Semiconductors #CapacitanceModeling #EmergingTechnologies #Teamwork

Great achievement! Congratulations Deven Hegade Patil!!

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