Semidynamics ha compartido esto
How can you reduce memory latency in your RISC-V design to zero? Cache is the typical solution for a processor that accesses data faster than memory can deliver it. But that doesn't solve all the issues. Semidynamics has developed Gazillion Misses, an IP block that works alongside their RISC-V processor core, to resolve this. Basically, it can maintain 128 in-flight memory requests while still allowing the processor to do useful work. But don't take my word for it—check out this interview with their CEO and founder, Roger Espasa.